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hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 1 hms81c2232/48, hms81c2332/48 cmos single-chip 8-bit microcontroller with vfd controller & vfd driver 1. overview 1.1 description the hms81c2232/48 is advanced cmos 8-bit micro-controller with 32/48k bytes of ro m(eprom). this is a po werful micro-controller which provides a highly flexible a nd cost effective solution to many vfd applicati ons. this provides the following standard fea tures : 32k/ 48k bytes of rom(eprom), 1k bytes of ra m, 8-bit timer/c ounter, 8-bit a/d converter, 6-bit wa tch dog timer, programmable buzzer driving port, serial peripheral in terface, 8-bit remote control t imer, on-chip oscillato r and clock circuitry. it also comes wi th high voltage i/o pins that can directly drive a vfd(va cuum fluorescent display). in addition, the hms8xc2232/48 support power saving modes t o reduce power consumption. 1.2 hms81c2232/48 features ? 32k/48k bytes rom(eprom) ? 896 bytes of on-chip data ram (including stack area) ? 112 bytes of on-chip display ram ? minimum instruction execution time: - 1us at 4mhz (2cyc le nop instruction) ? one 8-bit basic interval timer ? one 7-bit watch dog timer ? two 8-bit timer/counters ? 10-bit high speed pwm output ? two 8-bit serial peripheral interface ? two external interrupt ports ? one programmable 6-bit buzzer driving port ? 53 fip ports - 16ea output only pins - high-voltage pins max. 40v ? operating temperature -40c ~ 85c ? 12 interrupt sources - two external sources (int0, int1) - two timer/counter sources (timer0, timer1) - three remote timer sources(fe,re,ovf) - two spi sources(sio1, sio3) - three functional sources (adc,wdt,bit) ? 7-channel 8-bit on-chip analog to digital con- verter ? oscillator: - crystal - ceramic resonator ? low power dissipation modes - stop mode - sleep mode ? operating voltage: 2.7v ~ 5.5v (@8mhz) 4.5v ~ 5.5v (@10mhz) ? operating frequency: 1mhz ~ 10mhz ? enhanced ems improvement power fail processor (noise immunity circuit) device name rom size ram size display ram otp package hms81c2232 32k bytes 896 bytes 112bytes hms87c2232 80tqfp 80mqfp hms81c2248 48k bytes hms87c2248 hms81c2332 32k bytes 896 bytes 112bytes hms87c2332 64sdip,64lqfp 64mqfp hms81c2348 48k bytes hms87c2348
hms81c2232/48 hms81c2332/48 2 feb. 2003 ver 1.00 preliminary 1.3 hms2332/48 features ? 32k/48k bytes rom(eprom) ? 896 bytes of on-chip data ram (including stack area) ? 112 bytes of on-chip display ram ? minimum instruction execution time: - 1us at 4mhz (2cyc le nop instruction) ? one 8-bit basic interval timer ? one 7-bit watch dog timer ? two 8-bit timer/counters ? 10-bit high speed pwm output ? two 8-bit serial peripheral interface ? two external interrupt ports ? one programmable 6-bit buzzer driving port ? 41 fip ports - 12ea output only pins - high-voltage pins max. 40v ? operating temperature -40c ~ 85c ? 11 interrupt sources - two external sources (int0, int1) - two timer/counter sources (timer0, timer1) - three remote timer sources(fe,re,ovf) - one spi sources(sio1) - three functional sources (adc,wdt,bit) ? 5-channel 8-bit on-chip analog to digital con- verter ? oscillator: - crystal - ceramic resonator ? low power dissipation modes - stop mode - sleep mode ? operating voltage: 2.7v ~ 5.5v (@8mhz) 4.5v ~ 5.5v (@10mhz) ? operating frequency: 1mhz ~ 10mhz ? enhanced ems improvement power fail processor (noise immunity circuit) 1.4 development tools the hms81c22xx/23xx are supported by a full-featured macro assembler, an in-circuit emulator choice-dr. tm and otp pro- grammers. there are third different type programmers such as emulator add-on board type, singl e type, gang type. for mode de- tail, refer to ?25. otp pr ogramming? on page 112. macro assembler operates under the ms-windows 95, 98, nt, 2000, xp tm .please contact sales part of hynix semiconductor. in circuit emulators choice-dr. socket adapter for otp oa87c23xx-64sd (64sdip) oa87c23xx-64qf (64mqfp) oa87c23xx-64qt (64lqfp) oa87c22xx-80qf (80mqfp) oa87c22xx-80qt (64tqfp) pod chpod81c22d-64sd (64sdip) assembler hynix macro assembler
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 3 1.5 ordering information hms81c22xx device name ro m size ram size package mask version hms81c2232 q hms81c2232 tq hms81c2248 q hms81c2248 tq 32k bytes 32k bytes 48k bytes 48k bytes 896 bytes 80mqfp 80tqfp 80mqfp 80tqfp otp version hms81c2232 q hms81c2232 tq hms81c2248 q hms81c2248 tq 32k bytes otp 32k bytes otp 48k bytes otp 48k bytes otp 896 bytes 80mqfp 80tqfp 80mqfp 80tqfp hms81c23xx device name ro m size ram size package mask version hms81c2332 k hms81c2332 q hms81c2332 lq hms81c2348 k hms81c2348 q hms81c2348 lq 32k bytes 32k bytes 32k bytes 48k bytes 48k bytes 48k bytes 896 bytes 64sdip 64mqfp 64lqfp 64sdip 64mqfp 64lqfp otp version hms87c2332 k hms87c2332 q hms87c2332 lq hms87c2348 k hms87c2348 q hms87c2348 lq 32k bytes otp 32k bytes otp 32k bytes otp 48k bytes otp 48k bytes otp 48k bytes otp 896 bytes 64sdip 64mqfp 64lqfp 64sdip 64mqfp 64lqfp
hms81c2232/48 hms81c2332/48 4 feb. 2003 ver 1.00 preliminary 2. block diagram figure 2-1 hms81c2232/48 block diagram reset p00~p07 port0 port2 port3 port4 port5 port6 p20~p27 p30~p37 p40~p47 p50~p57 p60~p64 fip controller driver & system control fip00~fip23 fip24~fip31 fip32~fip39 fip40~fip47 fip48~fip52 v disp v dd2 x in x out 8-bit remote control timer 8-bit timer0 watchdog timer serial interface (sio3) 8-bit adc 8-bit timer1 serial interface (sio1) buzzer interrupt controller g80 cpu core rom (eprom) memory ram 896 bytes ti/p02 ec0/p63 pwm1o/p64 sck3/p20 so3/p21 so1/p25 si1/p26 sck1/p27 buzo/p07 ani0~ani6 av dd av ss intp0/p00 intp1/p01 v dd0 v dd1 v ss0 v ss1 bus
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 5 figure 2-2 hms81c2332/48 block diagram reset p00~p07 port0 port2 port3 port4 port5 port6 p24~p27 p30~p37 p40~p44 p50~p55 p62~p64 fip controller driver & system control fip00~fip18 fip24~fip31 fip32~fip36 fip40~fip45 fip50~fip52 v disp v dd2 x in x out 8-bit remote control timer 8-bit timer0 watchdog timer 8-bit adc 8-bit timer1 serial interface (sio1) buzzer interrupt controller g80 cpu core rom (eprom) memory ram 896 bytes ti/p02 ec0/p63 pwm1o/p64 so1/p25 si1/p26 sck1/p27 buzo/p07 ani0~ani4 av dd av ss intp0/p00 intp1/p01 v dd0 v dd1 v ss0 v ss1 bus
hms81c2232/48 hms81c2332/48 6 feb. 2003 ver 1.00 preliminary 3. pin assignment figure 3-1 hms81c2232/48 pin assignment high voltage port 80mqfp hms81c2232/48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 52 51 50 49 48 47 46 45 44 43 42 41 60 59 58 57 56 55 54 53 32 31 30 29 28 27 26 25 24 23 22 21 40 39 38 37 36 35 34 33 69 70 71 72 73 74 75 76 77 78 79 80 61 62 63 64 65 66 67 68 fip11 fip10 fip09 fip08 fip07 fip06 fip05 fip04 fip03 fip02 fip01 fip00 fip19 fip18 fip17 fip16 fip15 fip14 fip13 fip12 fip46 fip47 fip48 fip49 fip50 fip51 fip52 v dd0 av dd v ss0 p06 p05 fip38 fip39 fip40 fip41 fip42 fip43 fip44 fip45 fip26 fip27 fip28 fip29 fip30 fip31 fip32 fip33 fip34 fip35 fip36 fip37 v disp v dd2 fip20 fip21 fip22 fip23 fip24 fip25 p56 p57 p60 p61 p62 p46 p47 p50 p51 p52 p53 p54 p55 p63/ec0 p64/pwm1o ani3 ani2 r30 r31 r32 r33 r34 r35 r36 r37 r40 r41 r42 r43 r44 r45 v dd1 v ss1 x in x out p07 reset p27 p26 p25 p24 p23 p22 p21 p20 p00 p01 p02 av ss p03 p04 buzo sck1 si1 so1 ani6 ani5 ani4 so3 sck3 intp0 intp1 ti ani0 ani1 80tqfp hms81c2232/48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 52 51 50 49 48 47 46 45 44 43 42 41 60 59 58 57 56 55 54 53 32 31 30 29 28 27 26 25 24 23 22 21 40 39 38 37 36 35 34 33 69 70 71 72 73 74 75 76 77 78 79 80 61 62 63 64 65 66 67 68 fip11 fip10 fip09 fip08 fip07 fip06 fip05 fip04 fip03 fip02 fip01 fip00 fip19 fip18 fip17 fip16 fip15 fip14 fip13 fip12 fip46 fip47 fip48 fip49 fip50 fip51 fip52 v dd0 av dd v ss0 p06 p05 fip38 fip39 fip40 fip41 fip42 fip43 fip44 fip45 fip26 fip27 fip28 fip29 fip30 fip31 fip32 fip33 fip34 fip35 fip36 fip37 v disp v dd2 fip20 fip21 fip22 fip23 fip24 fip25 p56 p57 p60 p61 p62 p46 p47 p50 p51 p52 p53 p54 p55 p63/ec0 p64/pwm1o ani3 ani2 r30 r31 r32 r33 r34 r35 r36 r37 r40 r41 r42 r43 r44 r45 v dd1 v ss1 x in x out p07 reset p27 p26 p25 p24 p23 p22 p21 p20 p00 p01 p02 av ss p03 p04 buzo sck1 si1 so1 ani6 ani5 ani4 so3 sck3 intp0 intp1 ti ani0 ani1
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 7 figure 3-2 hms81c2332/48 64sd ip & 64mqfp pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 51 50 49 32 31 30 29 28 27 26 25 24 23 22 21 20 52 53 54 55 56 57 58 59 60 61 62 63 64 64mqfp 64sdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 high voltage port hms81c2332/48 hms81c2332/48 fip11 fip12 fip13 fip07 fip06 fip05 fip04 fip03 fip02 fip01 fip00 fip14 fip15 fip16 fip17 fip18 fip08 fip09 fip10 fip50 fip51 v dd0 av dd v ss0 p06 p05 fip40 fip41 fip42 fip43 fip44 fip45 p62 p50 p51 p52 p53 p54 p55 p63/ec0 p64/pwm1o ani3 ani2 fip26 fip27 fip28 fip29 fip30 fip31 fip32 fip33 fip34 fip35 fip36 v disp v dd2 fip24 fip25 p30 p31 p32 p33 p34 p35 p36 p37 p40 p41 p42 p43 p44 v dd1 v ss1 x in x out p07 reset p27 p26 p25 p24 p00 p01 p02 av ss p03 p04 buzo sck1 si1 so1 ani6 intp0 intp1 ti ani0 ani1 fip52 fip07 fip06 fip05 fip04 fip03 fip02 fip01 fip10 fip09 fip08 fip13 fip12 fip11 fip14 fip15 fip16 fip17 fip18 fip26 fip27 fip28 fip29 fip30 fip31 fip32 fip33 fip34 fip35 v disp v dd2 fip24 fip25 p30 p31 p32 p33 p34 p35 p36 p37 p40 p41 p42 p43 fip40 fip41 fip42 fip43 fip44 fip45 p50 p51 p52 p53 p54 p55 fip36 p44 fip50 fip51 v dd0 av dd v ss0 p62 p63/ec0 p64/pwm1o fip52 p06 p05 ani3 ani2 v dd1 v ss1 x in x out p07 reset p27 p26 p25 p24 p00 p01 p02 av ss p03 p04 buzo sck1 si1 so1 ani6 intp0 intp1 ti ani0 ani1 fip00
hms81c2232/48 hms81c2332/48 8 feb. 2003 ver 1.00 preliminary figure 3-3 hms81c2332/48 64lqfp pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 64lqfp high voltage port hms81c2332/48 p05 p06 ani2 ani3 fip00 fip07 fip06 fip05 fip04 fip03 fip02 fip01 fip10 fip09 fip08 fip13 fip12 fip11 fip40 fip41 fip42 fip43 fip44 fip45 p50 p51 p52 p53 p54 p55 fip36 p44 fip50 fip51 v dd0 av dd v ss0 p62 p63/ec0 p64/pwm1o fip52 fip15 fip14 v dd1 v ss1 x in x out p07 reset p27 p26 p25 p24 p00 p01 p02 av ss p03 p04 buzo sck1 si1 so1 ani6 intp0 intp1 ti ani0 ani1 fip35 p43 fip16 fip17 fip18 fip26 fip27 fip28 fip29 fip30 fip31 fip32 fip33 fip34 v disp v dd2 fip24 fip25 p30 p31 p32 p33 p34 p35 p36 p37 p40 p41 p42
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 9 4. package diagram figure 4-1 hms81c2232/48 package diagram 14.20 13.80 17.40 17.00 17.40 17.00 14.20 13.80 see detail "a" 1.00 0.60 0-7 0.36 0.10 0.20 0.10 1.8 detail "a" unit: mm 80tqfp (14x14) 1.70 max. 0.38 0.24 0.65(t.p) 1.4 14.20 13.80 17.40 17.00 17.40 17.00 14.20 13.80 see detail "a" 1.00 0.60 0-7 0.36 0.10 0.25 0.10 1.8 detail "a" unit: mm 80mqfp (14x14) 3.0 max. 0.38 0.24 0.65(t.p) 1.4
hms81c2232/48 hms81c2332/48 10 feb. 2003 ver 1.00 preliminary figure 4-2 hms81c2332/48 64sdi p & 64mqfp package diagram unit: inch 2.280 2.260 0.022 0.016 0.050 0.030 0.070 bsc 0.140 0.120 min. 0.015 0.680 0.660 0.750 bsc 0-15 64sdip 0 . 0 1 2 0 . 0 0 8 0.205 max. 20.10 19.90 24.15 23.65 18.15 17.65 14.10 13.90 3.18 max. 0.50 0.35 1.00 bsc see detail "a" 1.03 0.73 0-7 0.36 0.10 0.23 0.13 1.95 ref detail "a" unit: mm 64mqfp
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 11 figure 4-3 hms81c2332/48 64lqfp package diagram 1.60 max. see detail "a" 0.75 0.45 0-7 0.15 0.05 1.00 ref detail "a" unit: mm 10.00 bsc 12.00 bsc 12.00 bsc 10.00 bsc 0.38 0.22 0.50 bsc 1.45 1.35 64lqfp
hms81c2232/48 hms81c2332/48 12 feb. 2003 ver 1.00 preliminary 5. pin function 5.1 p00 ~ p07 (port 0) p00 through p07 are used as a 8-b it i/o port. these pins also have external interrupt request input an d timer input func tions in addi- tion to the i/o port function. port 0 can be set in the following op- eration modes in 1-bit units. (1) port mode p00 through p07 function as a 8-bit i/o port in this mode. this 2- bit port can be set in the input or output mode in 1-bit units by the port 0 direction register (p0io). wh en used as an input port, the internal pull-up resistor can be connected by using the pull-up re- sistor option register0 (pu0). (2) alternate mode p00 through p01 functions as extern al interrupt request input and p02 functions as timer input pin. p03 through p06 functions as adc input pin and p07 functions as buzzer dirver output pin. (a) intp0, intp1 intp0 and intp1 input external interrupt requests whose valid edge can be specified (to be the rising edge, falling edge, or both the rising and falling edges). (b) ti ti input timer of the 8-bit remote control timer. (c) ani0, ani1, andi2, ani3 these are input pins of the a/d converter. (d) buzo this is a output pin of buzzer dirver output. 5.2 p20 ~ p27 (port 2) p20 through p27 constitute an 8- bit i/o port, port 2. these pins also have functions to input/output data of the serial interface, clock, and automatic transmit/rec eive busy input. the following operation modes can be sp ecified in 1-bit units. (1) port mode in this mode, p20 through p27 func tion as an 8-bit i/o port. this port can be set in the input or out put mode in 1-bit units by using the port 2 direction register (p2io) . when the port is used as an input port, the internal pullup resistor can be used if so specified by the pull-up resistor option register 2 (pu2). (2) altern ate mode in this mode, p20 through p21 are used to output serial interface data, clock. p22 through p24 fu nctions as adc input pin. p25 through p27 are used to input/output serial interface data, clock. (a) si1, so1, so3 these are i/o pins of the serial data of the serial interface. (b) sck1, sck3 these are i/o pins of the serial clock of the serial interface. (c) ani4, ani5, ani6 these are input pins of the a/d converter. 5.3 p30 ~ p37 (port 3) p30 through p37 constitute an 8-bi t output port. these pins are also used as fip controller/driver output pins. the following op- eration modes can be sp ecified in 1-bit units. (1) port mode p30 through p37 function as an 8- bit output port in this mode. these pins are p-ch open-drain pins. pull-down resistors can be connected to these pins of th e mask rommodels by mask option. the hms87c2232/48 does not have pull-down resistors. (2) altern ate mode in this mode, p30 through p37 f unction as the output pins of the fip controller/driver (fip24 through fip31). port pin alternate function p00 p01 p02 p03 p04 p05 p06 p07 intp0 (external interrupt 0) intp1 (external interrupt 1) ti (timer input of remote control timer) ani0 (analog input 0) ani1 (analog input 1) ani2 (analog input 2) ani3 (analog input 3) buzo (buzzer driver output) port pin alter nate function p20 p21 p22 p23 p24 p25 p26 p27 sck3 (serial3 clock input/output) so3 (serial3 data output) ani4 (analog input 4) ani5 (analog input 5) ani6 (analog input 6) so1 (serial1 data output) si1 (serial1data input) sck1 (serial1 clock input/output) port pin alter nate function p30~p37 fip24-fip31
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 13 5.4 p40 ~ p47 (port 4) p40 through p47 constitute an 8- bit output port. these pins are also used as fip controller/drive r output pins. the following op- eration modes can be sp ecified in 1-bit units. (1) port mode p40 through p47 function as an 8-bit output port in this mode. these pins are p-ch open-drain pins. pull-down resistors can be connected to these pins of th e mask rom models by mask op- tion. the hms87c2232/48 does not have pull-down resistors. (2) alternate mode in this mode, p40 through p47 func tion as the output pins of the fip controller/driver (fip32 through fip39). 5.5 p50 ~ p57 (port 5) p50 through p57 constitute an 8-bi t i/o port. these pins are also used as fip controller/driver out put pins. the following operation modes can be specified in 1-bit units. (1) port mode p50 through p57 function as an 8-bit i/o port in this mode. these pins are p-ch open-drain pins. pull-down resistors can be con- nected to these pins of the mask rom models by mask option. pull-down resistor to v disp or v ss0 can be selected in 1-bit units. the hms87c2232/48 does not have pul l-down resistors. (2) alternate mode in this mode, p50 through p57 func tion as the output pins of the fip controller/driver (fip40 through fip47). 5.6 p60 ~ p64 (port 6) p60 through p64 constitute a 5-bit i/o port. these pins are also used as fip controller/driver out put pins. the following operation modes can be specified in 1-bit units. (1) port mode p60 through p64 function as a 5-bit input/output port in this mode. these pins are p-ch open-d rain pins. pull-down resistors can be connected to these pins of the mask rom models by mask option. pull-down resistor to v disp or v ss0 can be selected in 1- bit units. the hms87c2232/48 does not have pull-down resis- tors. (2) altern ate mode in this mode, p60 through p64 f unction as the output pins of the fip controller/driver (fip48 through fip52). (a) ec0 this is input pin of the event counter0. (b) pwm1o this is outinput pin of the pwm. 5.7 fip0 ~ fip23 these are the output pins of the fip controller/driver. 5.8 v disp this pin connects a pull-down resist or to the fip controller/driv- er. 5.9 av dd this pin supply an analog voltage to the a/d converter. always keep this pin at the same potential as the v dd1 pin even when the a/d converter is not used. 5.10 av ss this is the ground pin of the a/d converter. always keep this pin at the same potential as the v ss1 pin even when the a/d convert- er is not used. 5.11 /reset this pin inputs an active-l ow system reset signal. 5.12 x in and x out these pins connect a crystal resonator for main system clock os- cillation. to supply an exte rnal clock, input it to x in , and input a signal reverse to that input to x in , to x out . 5.13 ani0 through ani6 these are the input pins of the a/d converter. port pin alternate function p40~p47 fip32-fip39 port pin alternate function p50~p57 fip40-fip47 port pin alter nate function p60 p61 p62 p63 p64 fip48 fip49 fip50 fip51 / ec0 fip52 / pwm1o
hms81c2232/48 hms81c2332/48 14 feb. 2003 ver 1.00 preliminary 5.14 v dd0 ~ v dd2 v dd0 supplies a positive voltage to the ports. v dd1 supplies a positive voltage to the internal function blocks other than the ports, analog block, and fip controller/driver. v dd2 supplies a positive voltage to the fip controller/driver. 5.15 v ss0 and v ss1 v ss0 is the ground pin for the ports. v ss1 is the ground pin for the internal function blocks other than the ports and analog block. pin name in/out function basic alternate p00 (intp0) i/o (i) port0 8-bit i/o ports can be set in input or output mode in 1-bit units. internal pull-up resistor can be used via software when this port is used as input port external interrupt 0 input p01 (intp1) i/o (i) external interrupt 1 input p02 (ti) i/o (i) timer input of 8-bit remote control timer p03 (ani0) i/o (i) analog input channel 0 for a/d converter p04 (ani1) i/o (i) analog input channel 1 for a/d converter p05 (ani2) i/o (i) analog input channel 2 for a/d converter p06 (ani3) i/o (i) analog input channel 3 for a/d converter p07 (buzo) i/o (o) buzzer driving output p20 (sck3) i/o (i/o) port2 8-bit i/o ports can be set in input or output mode in 1-bit units. internal pull-up resistor can be used via software when this port is used as input port serial3 clock input/output p21 (so3) i/o (o) serial3 data output p22 (ani4) i/o (i) analog input channel 4 for a/d converter p23 (ani5) i/o (i) analog input channel 5 for a/d converter p24 (ani6) i/o (i) analog input channel 6 for a/d converter p25 (so1) i/o (o) serial1 data output p26 (si1) i/o (i) serial1data input p27 (sck1) i/o (i/o) serial1clock input/output fip0~fip23 o high voltage high-current of fip controller/driver - p30~p37 (fip24-fip31) o port3 p-ch open-drain 8-bit high-voltage output port. pull-down resistor for v disp or v ss0 can be used by mask option in 1-bit units(mask rom models only) otp models do not have pull-down resistor fip24-fip31 p40~p47 (fip32-fip39) o port4 p-ch open-drain 8-bit high-voltage output port. pull-down resistor for v disp or v ss0 can be used by mask option in 1-bit units(mask rom models only) otp models do not have pull-down resistor fip32-fip39 table 5-1 hms81c2232/48 po rt function description
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 15 p50~p57 (fip40-fip47) i/o (o) port5 p-ch open-drain 8-bit high-voltage output port. can be set in input or output mode in 1-bit units. when it is used as input port, set the output latch to ?0?, and read port level read(p50 through p57). pull-down resistor for v disp or v ss0 can be used by mask option in 1-bit units(mask rom models only). otp models do not have pull-down resistor. fip40-fip47 p60 i/o (o) port6 p-ch open-drain 8-bit high-voltage output port. can be set in input or output mode in 1-bit units. when it is used as input port, set the output latch to ?0?, and read port level read(p50 through p57). pull-down resistor for v disp or v ss0 can be used by mask option in 1-bit units(mask rom models only). otp models do not have pull-down resistor. fip48 p61 i/o (o) fip49 p62 i/o (o) fip50 p63 i/o (i/o) fip51/ec0 p64 i/o (o) fip52/timer1 pwm 1 pulse output av dd - analog power/reference voltage input to a/d converter set the same potential as v dd av ss - ground potential for a/d converter. set the same potential as v dd v dd0 - positive power supply to ports v ss0 - ground potential to ports. v dd1 - positive power supply to internal function block v ss1 - ground potential(except ports, analog block) v dd2 - positive power supply to fip controller/driver. v disp - pull-down resistor connection of fip controller/driver reset i system reset signal input xin i main system cloc k oscillation input xout o main system cloc k oscillation output pin name in/out function basic alternate table 5-1 hms81c2232/48 po rt function description
hms81c2232/48 hms81c2332/48 16 feb. 2003 ver 1.00 preliminary 6. port structures p00~p01/intp0~intp1, p02/ti, p26/si1 p03~p06/an0~an3, p22~p24/an4~an6 p20/sck3, p27/sck1 p21/so3, p25/so1, p07/buzo data bus v dd0 v ss0 pin data reg. direction reg. rd intp1,intp2 ti, si1 alternate function pull-up tr. pull-up reg. mux v dd0 noise filter data bus v dd v ss pin data reg. direction reg. rd v dd a/d analog converter input mode a/d ch. selection pull-up tr. pull-up reg. mux data bus v dd0 v ss0 pin data reg. direction reg. rd sck3(in) sck1(in) alternate function pull-up tr. pull-up reg. mux v dd0 noise filter sck3(out) sck1(out) data bus v dd0 v ss0 pin data reg. direction reg. rd pull-up tr. pull-up reg. mux v dd0 so3,si1 buzo
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 17 fip00~fip23 p30~37/fip24~fip31, p40~47/fip32~fip39 p50~p57/fip40~fip47, p60~p64/fip48~fip52 reset xin, xout pin v dd2 vdisp data bus mask option fip digit/segment mask option otp not connected pin data reg. v dd2 data bus fip digit/segment mask option otp not connected vdisp mask option vss0 pin data reg. rd v dd2 vdisp data bus mask option vss0 port level read reg. fip digit/segment mask option otp not connected reset v dd0 v ss0 otp :disconnected main :connected mask option otp not connected v dd0 xout v dd xin stop mainclk off v ss
hms81c2232/48 hms81c2332/48 18 feb. 2003 ver 1.00 preliminary 7. electrical characteristics 7.1 absolute maximum ratings note: stresses above those listed under ?absolute maxi- mum ratings? may cause permanent damage to the de- vice. this is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability. 7.2 recommended operating conditions parameter symbol specifications unit min. max. supply voltage v dd -0.3 6.0 v av dd v dd -0.3 v dd +0.3 v av ss -0.3 0.3 v v disp v dd -45 v dd +0.3 v normal voltage pin v i1 -0.3 v dd +0.3 v v o1 -0.3 v dd +0.3 v i oh1 -8 ma i oh1 -30 ma i ol1 15 ma i ol1 50 ma hige voltage pin v i2 v dd -45 v dd +0.3 v v o2 v dd -45 v dd +0.3 v i oh2 -30 ma i oh2 -120 ma total power dissipation pt 700 mw storage temperature tstg -40 125 c parameter symbol condition specifications unit min. max. supply voltage v dd f xi = 5 mhz 2.7 5.5 v operating frequency f xin v dd = 2.7v~5.5v 110mhz operating temperature t opr v dd = 2.7v~5.5v -40 85 c
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 19 7.3 a/d converter characteristics (t a =25 c, v dd =5v, v ss =0v, av dd =5.12v, av ss =0v @ f xin =5mhz) parameter symbol condition specifications unit min. typ. 1 1. data in ?typ? column is at 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. max. analog power supply input voltage range av dd av ss - av dd v analog input voltage range v an av ss av dd v current following between av dd and av ss i avdd - - 200 ua overall accuracy ca in -- 2lsb non-linearity error n nle -- 2lsb differential non-linearity error n dnle -- 2lsb zero offset error n zoe -- 2lsb full scale error n fse -- 2lsb gain error n nle -- 2lsb conversion time t conv f xin =4mhz - - 30 us
hms81c2232/48 hms81c2332/48 20 feb. 2003 ver 1.00 preliminary 7.4 dc electrical characteristics (v dd = 5.0v 10%, v ss = 0v, t a = -40 ~ 85c, f xin = 5 mhz, vdisp = v dd -40v to v dd ) , parameter symbol pin test condition specification unit min typ. 1 max input high voltage v ih1 xin external clock 0.9v dd v dd +0.3 v v ih2 reset ,si1,intp0,intp1,ti, sck1,ec0 0.8v dd v dd +0.3 v ih3 p00~p07,p20~p27,p50~p57 p60~p64 0.7v dd v dd +0.3 input low voltage v il1 xin external clock -0.3 0.1v dd v v il2 reset ,si1,intp0,intp1,ti, sck1,ec0,sck3 -0.3 0.2v dd v il3 p00~p07,p20~p27 -0.3 0.3v dd v il4 p50~p57,p60~p64 0.3v dd output high voltage v oh1 p00~p07,p20~p27 i oh = -1.0ma v dd -1.0 v dd v p00~p07,p20~p27 i oh = -100ua v dd -0.5 v dd v oh2 xout i oh = -50ua v dd -2.0 v dd output low voltage v ol1 p00~p07,p20~p27 i ol = 400ua 00.5v v ol2 xout i ol = 50ua 02 input high leakage current i ih1 p00~p07,p20~p27,p50~p57 p60~p64,reset v in = v dd 1ua input low leakage current i il1 p00~p07,p20~p27,p50~p57 p60~p64,reset v in = 0 -1 ua i il2 p50~p57,p60~p64 v in = v dd -40v -10 input pull-up resistor(*option) r pu p00~p07,p20~p27 v dd =5v 10 60 100 k ? osc feed back resistor r fb xin, xout v dd =5v 0.25 2.5 m ? vfd output current i od1 fip00~fip19 v od =v dd -2v -15 ma i od2 fip20~fip52 v od =v dd -2v -5 ma on-chip mask option pull-down resistance r d1 p50~p57,p60~p64 v ss0 connection 15 35 90 k ? r d2 fip00~fip52 v disp connection v dd -v disp =40v 30 60 135 k ? power fail detect voltage v pfd v dd 2.7 v current dissipation in active mode i dd v dd f xin =5mhz 5 10 ma current dissipation in sleep mode i sleep v dd f xin =5mhz 2 3 ma
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 21 current dissipation in stopo mode i stop v dd f xin =off 1 10 ua internal rc wdt frequency t rcwdt xout 8 30 khz 1. data in ?typ.? column is at 4.5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested.
hms81c2232/48 hms81c2332/48 22 feb. 2003 ver 1.00 preliminary 7.5 ac characteristics (t a =-40~ 85 c, v dd =5v 10%, v ss =0v) figure 7-1 timing chart parameter symbol pins specifications unit min. typ. max. operating frequency f cp xin 1 - 10 mhz system clock cycle time t sys - 200 2000 ns oscillation stabilizing time t st xin, xout - - 20 ms external clock pulse width t cpw xin 40 - - ns external clock transition time t rcp, t fcp xin - - 10 ns interrupt input pulse width t epw intp0, intp1 2 - - t sys event counter input pulse width t ecw ec0 2 t sys event counter transition time t rep, t fep ec0 - - 20 ns reset input width t rst reset 8- - t sys t rcp t fcp xi 0.5v v dd -0.5v 0.2v dd reset 0.2v dd 0.8v dd intp0 t rst t ecw t ecw 1/f cp t cpw t cpw t sys t rep t fep 0.2v dd 0.8v dd t epw t epw ec0 intp1 ti
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 23 7.6 ac characteristics (t a =-40~+85 c, v dd =5v 10%, v ss =0v, f xin =4mhz) figure 7-2 serial i/o timing chart parameter symbol pins specifications unit min. typ. max. serial input clock pulse t scyc sck1, sck3 2t sys +200 --ns serial input clock pulse width t sckw sck1, sck3 t sys +70 --ns serial input clock pulse transition time t fsck t rsck sck1, sck3 - - 30 ns serial output clock cycle time t scyc sck1, sck3 4t sys - 16t sys ns serial output clock pulse width t sckw sck1, sck3 2t sys -30 ns serial output clock pulse transition time t fsck t rsck sck1, sck3 30 ns serial output delay time t ds so 100 ns si input pulse transition time t fsin t rsin si1 - - 30 ns si input setup time (external sck) t sus si1 100 - - ns si input setup ti me (internal sck) t sus si1 200 - ns si input hold time t hs si1 t sys +100 -ns sck si 0.2v dd so 0.2v dd 0.8v dd t scyc t sckw t sckw t rsck t fsck 0.8v dd t sus t hs t ds 0.2v dd 0.8v dd t rsin t fsin
hms81c2232/48 hms81c2332/48 24 feb. 2003 ver 1.00 preliminary 7.7 typical characteristics this graphs and tables provided in this section are for design guidance only and are not tested or guaranteed. in some graphs or tables the data presented are out- side specified operating ra nge (e.g. outside specified v dd range). this is for information only and devices are guaranteed to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. ?typ- ical? represents the mean of the distribution while ?max? or ?min? represents (mean + 3 ) and (mean ? 3 ) respectively where is standard deviation i oh ? v oh -12 -9 -6 -3 0 12 34 5 (v) ta=25 c v dd =5.0v (ma) i oh v oh i oh ? v oh -12 -9 -6 -3 0 12 34 5 (v) ta=25 c v dd =4.0v (ma) i oh v oh i oh ? v oh -12 -9 -6 -3 0 12 34 5 (v) ta=25 c v dd =3.0v (ma) i oh v oh i ol ? v ol 40 30 20 10 0 0.5 1 1.5 2 2.5 (v) ta=25 c v dd =5.0v (ma) i ol v ol i ol ? v ol 40 30 20 10 0 0.5 1 1.5 2 2.5 (v) ta=25 c v dd =4.0v (ma) i ol v ol i ol ? v ol 40 30 20 10 0 0.5 1 1.5 2 2.5 (v) ta=25 c v dd =3.0v (ma) i ol v ol i oh ? v oh -40 -30 -20 -10 0 12 34 5 (v) (ma) i oh v oh i oh ? v oh -40 -30 -20 -10 0 12 34 5 (v) (ma) i oh v oh i oh ? v oh -40 -30 -20 -10 0 12 34 5 (v) (ma) i oh v oh p00~p07, p20~p27 pins fip00~fip52 pins ta=25 c v dd =5.0v ta=25 c v dd =4.0v ta=25 c v dd =3.0v p00~p07, p20~p27 pins
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 25 ta=25 c i dd ? v dd 4.0 3.0 2.0 1.0 0 (ma) i dd 23 45 6 v dd (v) normal operation i stop ? v dd 2.0 1.5 1.0 0.5 0 ( a) i dd 23 45 6 v dd (v) stop mode 85 c 25 c -20 c f xin = 4.5mhz 2.5mhz ta=25 c i sby ? v dd 4.0 3.0 2.0 1.0 0 (ma) i dd 23 45 6 v dd (v) stand-by mode f xin = 4.5mhz 2.5mhz v dd ? v il2 4 3 2 1 0 (v) v il2 23 45 6 v dd (v) v dd ? v il1 4 3 2 1 0 (v) v il1 23 45 6 v dd (v) ta=25 c 1 f xin =4.5mhz ta=25 c f xin =4.5mhz v dd ? v il3 4 3 2 1 0 (v) v il3 23 45 6 v dd (v) ta=25 c 1 f xin =4.5mhz reset , int0, int1, ec0 pins xin, sxin pins r03~p07, r20~p27 pins v dd ? v ih2 4 3 2 1 0 (v) v ih2 23 45 6 v dd (v) v dd ? v ih1 4 3 2 1 0 (v) v ih1 23 45 6 v dd (v) ta=25 c 1 f xin =4.5mhz ta=25 c f xin =4.5mhz v dd ? v ih3 4 3 2 1 0 (v) v ih3 23 45 6 v dd (v) ta=25 c 1 f xin =4.5mhz reset , int0, int1, ec0 pins xin, sxin pins r03~p07, p20~p27 pins
hms81c2232/48 hms81c2332/48 26 feb. 2003 ver 1.00 preliminary 8. memory organization the hms81c2232/48 have separate address spaces for program memory and data memory. progr am memory can only be read, not written to. it can be up to 32k/48k bytes of program memory. data memory can be read and wr itten to up to 448 bytes including the stack area. 8.1 registers this device has six registers th at are the program counter (pc), a accumulator (a), two index regi sters (x, y), the stack pointer (sp), and the program status word (psw). the program counter consists of 16-bit register. figure 8-1 configuration of registers accumulator: the accumulator is the 8-bit general purpose reg- ister, used for data operation such as transfer, temporary saving, and conditional judgement, etc. the accumulator can be used as a 16-bit register with y register as shown below. figure 8-2 configuration of ya 16-bit register x, y registers : in the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. these modes are extremely ef- fective for referencing subroutine tables and memory tables. the index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumula- tors. stack pointer : the stack pointer is an 8-bit register used for oc- currence interrupts and calling out subroutines. stack pointer identifies the location in the stack to be access (save or restore). generally, sp is automatically updated when a subroutine call is executed or an interrupt is accepted. however, if it is used in ex- cess of the stack area permitted by the data memory allocating configuration, the user-pro cessed data may be lost. the stack can be located at any position within 100 h to 1ff h of the internal data memory. the sp is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. normally, the initial value of ?ff h ? is used. note: the stack pointer must be initialized by software be- cause its value is undefined after reset. example: to initialize the sp ldx #0ffh txsp ; sp ff h program counter : the program counter is a 16-bit wide which consists of two 8-bit registers, pch and pcl. this counter indi- cates the address of the next inst ruction to be executed. in reset state, the program counter ha s reset routine address (pc h :0ff h , pc l :0fe h ). program status word : the program status word (psw) con- tains several bits that reflect the current state of the cpu. the psw is described in figure 8-3. it contains the negative flag, the overflow flag, the break flag the half carry (for bcd opera- tion), the interrupt enable flag, th e zero flag, and the carry flag. [carry flag c] this flag stores any carry or borrow from the alu of cpu after an arithmetic operation and is al so changed by the shift instruc- tion or rotate instruction. [zero flag z] this flag is set when the result of an arithmetic operation or data transfer is "0" and is cl eared by any other result. accumulator x register y register stack pointer program counter program status word x a sp y pcl psw pch two 8-bit registers can be used as a "ya" 16-bit register y a y a sp 01 h stack address ( 100 h ~ 1fe h ) bit 15 bit 0 87 hardware fixed 00 h ~ff h
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 27 figure 8-3 psw (program status word) register [interrupt disable flag i] this flag enables/disables all interrupts except interrupt caused by reset or software brk instruct ion. all interrupts are disabled when cleared to ?0?. this flag immediately becomes ?0? when an interrupt is served. it is set by the ei instruction and cleared by the di instruction. [half carry flag h] after operation, this is set when there is a carry from bit 3 of alu or there is no borrow from bit 4 of alu. this bit can not be set or cleared except clrv instru ction with overflow flag (v). [break flag b] this flag is set by software brk instruction to distinguish brk from tcall instruction with the same vector address. [direct page flag g] this flag assigns ram page for di rect addressing mode. in the di- rect addressing mode, addressi ng area is from zero page 00 h to 0ff h when this flag is "0". if it is set to "1", addressing area is assigned 100 h to 1ff h . it is set by setg instruction and cleared by clrg. [overflow flag v] this flag is set to ?1? when an overflow occurs as the result of an arithmetic operation involving signs. an overflow occurs when the result of an addition or subtraction exceeds +127(7f h ) or - 128(80 h ). the clrv instruction clears the overflow flag. there is no set instruction. when the bi t instruction is executed, bit 6 of memory is copied to this flag. [negative flag n] this flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. when the bit instruction is exe- cuted, bit 7 of memory is copied to this flag. n negative flag v g b h i z c msb lsb reset value : 00 h psw overflow flag brk flag carry flag receives zero flag interrupt enable flag carry out half carry fl ag receives carry out from bit 1 of addition operlands select direct page when g=1, page is selected to ?page 1?
hms81c2232/48 hms81c2332/48 28 feb. 2003 ver 1.00 preliminary figure 8-4 stack operation at execution of a call/tcall/pcall pcl pch 01fb sp after execution sp before execution 01fc 01fc 01fd 01fe 01fe push down at acceptance of interrupt pcl pch 01fb 01fb 01fc 01fd 01fe 01fe push down psw at execution of ret instruction pcl pch 01fb 01fe 01fc 01fd 01fe 01fc pop up at execution of ret instruction pcl pch 01fb 01fe 01fc 01fd 01fe 01fb pop up psw 0100h 01feh stack depth at execution of push instruction a 01fb 01fd 01fc 01fd 01fe 01fe push down sp after execution sp before execution push a (x,y,psw) at execution of pop instruction a 01fb 01fe 01fc 01fd 01fe 01fd pop up pop a (x,y,psw)
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 29 8.2 program memory a 16-bit program counter is capable of addressing up to 64k bytes, but this device has 32/48k bytes program memory space only physically implemented. ac cessing a location above ffff h will cause a wrap-around to 0000 h . figure 8-5, shows a map of program memory. after reset, the cpu begins execution from reset v ector which is stored in ad- dress fffe h and ffff h as shown in figure 8-6. as shown in figure 8-5, each ar ea is assigned a fixed location in program memory. program memory area contains the user pro- gram. figure 8-5 program memory map page call (pcall) area contai ns subroutine program to reduce program byte length by using 2 bytes pcall instead of 3 bytes call instruction. if it is frequen tly called, it is more useful to save program byte length. table call (tcall) causes the cpu to jump to each tcall ad- dress, where it commences the execution of the service routine. the table call service area sp aces 2-byte fo r every tcall: 0ffc0 h for tcall15, 0ffc2 h for tcall14, etc., as shown in figure 8-7. example: usage of tcall the interrupt causes the cpu to jump to specific location, where it commences the execution of the service routine. the external interrupt 0, for example, is assigned to location 0fffa h . the in- terrupt service locations sp aces 2-byte interval: 0fff8 h and 0fff9 h for external interrupt 1, 0fffa h and 0fffb h for exter- nal interrupt 0, etc. any area from 0ff00 h to 0ffff h , if it is not going to be used, its service location is availabl e as general purpose program mem- ory. figure 8-6 interrupt vector area interrupt vector area 8000 h feff h ff00 h ffc0 h ffdf h ffe0 h ffff h pcall area 4000 h tcall area hms81c2232, 32k rom hms81c2248, 48k rom lda #5 tcall 0fh ; 1byte instruction :; instead of 3 bytes :; normal call ; ;table call routine ; func_a: lda lrg0 ret ; func_b: lda lrg1 ret ; ;table call add. area ; org 0ffc0h ; tcall address area dw func_a dw func_b 1 2 0ffe0h e2 address vector area memory e4 e6 e8 ea ec ee f0 f2 f4 f6 f8 fa fc fe basic interval timer watchdog timer interrupt a/d converter interrupt - - timer/counter0 interrupt serial communication interface 3 remote control timer1 interrupt (falling edge) serial communication interface 1 external interrupt 1 external interrupt 0 reset vector area remote control timer0 interrupt (rising edge) - "-" means reserved area. note: remote control timer2 interrupt (overflow) key scan interrupt timer/counter1 interrupt
hms81c2232/48 hms81c2332/48 30 feb. 2003 ver 1.00 preliminary figure 8-7 pcall and tcall memory area pcall rel 4f35 pcall 35h tcall n 4a tcall 4 0ffc0 h c1 address program memory c2 c3 c4 c5 c6 c7 c8 0ff00 h address pcall area memory 0ffff h pcall area (256 bytes) * means that the brk software interrupt is using same address with tcall0. note: tcall 15 tcall 14 tcall 13 tcall 12 tcall 11 tcall 10 tcall 9 tcall 8 tcall 7 tcall 6 tcall 5 tcall 4 tcall 3 tcall 2 tcall 1 tcall 0 / brk * c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df 4f ~ ~ ~ ~ next 35 0ff35 h 0ff00 h 0ffff h 11111111 11010110 01001010 pc: fh fh dh 6h 4a ~ ~ ~ ~ 25 0ffd6 h 0ff00 h 0ffff h d1 next 0ffd7 h ? ? ? 0d125 h reverse
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 31 example: the usage softwa re example of vector address for hms81c2232/48. ;************************************************************************; ; interrupt vector table ; ;************************************************************************; org 0ffe0h dw not_used ; basic interval timer dw not_used ; watch dog timer dw not_used ; a/d converter dw not_used ; not usedr dw not_used ; not used dw timer1_isr ; timer1 dw not_used ; timer0 dw not_used ; sio3 dw spi_isr ; sio1 dw not_used ; key scan interrupt dw not_used ; remote timer2(overflow) dw not_used ; remote falling edge dw not_used ; remote rising edge dw not_used ; ext.int1 dw int0_isr ; ext.int0 dw reset ; reset ;************************************************************************; ; program initial part ; ;************************************************************************; org04000h ;hms81c2248/2348 program start reset: di ;disable all interrupt ;=====================; ; ram clear routine ; ;=====================; ldx #0 ldy #0 ram_clear0: lda #0 ;page0 ram clear(0000h ~ 00bfh) sta {x}+ cmpx #0c0h bne ram_clear0 inc y sty !rpr ;page select setg ldx #0 ram_clear1: lda #0 sta {x}+ cmpx #00h bne ram_clear1 inc y cmpy #5 ;page1~4 ram clear(0100h ~ 03ffh) bcs ram_clear_bye sty !rpr setg ; bra ram_clear1 ram_clear_bye: clrg ;page0 select ldx #0ffh ;initial stack pointer txsp call initial_io ;i/o port initial call initial_reg ;register initial ei ;enable interrupt ;******************************************************************************; ; main program part ; ;******************************************************************************; main: bra main
hms81c2232/48 hms81c2332/48 32 feb. 2003 ver 1.00 preliminary 8.3 data memory figure 8-8 shows the internal data memory space available. data memory is divided into three groups, a user ram (including stack), control registers and fip display memory. figure 8-8 data memory map user memory the hms81c2232/48 has 896 8 bits for the user memory (ram). ram pages are seleted by rpr. note: after setting rpr(ram page slect register), be sure to execute setg instru ction. when executing clrg instruction, be selected page0 regardless of rpr. control registers the control registers are used by the cpu and peripheral function blocks for controlling the desire d operation of the device. there- fore these registers contain control and status bits for the interrupt system, the timer/ counters, anal og to digital converters and i/o ports. the control registers are in address range of 0c0 h to 0ff h . note that unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in general return ran- dom data, and write accesses will have an indete rminate effect. more detailed informations of ea ch register are explained in each peripheral section. note: write only registers can not be accessed by bit ma- nipulation instruction. do not use read-modify-write instruc- tion. use byte manipulation instruction, for example ?ldm?. example; to write at ckctlr ldm clctlr,#09h ;divide ratio( 16 ) stack area the stack provides the area where the return address is saved be- fore a jump is performed during the processing routine at the ex- ecution of a subroutine call in struction or the acceptance of an interrupt. when returning from the processi ng routine, executing the sub- routine return instruction [ret] re stores the contents of the pro- gram counter from the stack; executing the interrupt return instruction [reti] restores the c ontents of the program counter and flags. the save/restore locations in the stack are determined by the stack pointed (sp). the sp is au tomatically decreased after the saving, and increased before the restoring. this means the value of the sp indicates the stack lo cation number for the next save. refer to figure 8-4 on page 28. figure 8-9 rpr(ram page select register) user memory control registers 0000 h 00bf h 00c0 h page0 page1 when ?g-flag=0?, this page is selected or stack area user memory user memory user memory not used fip display memory page2 page3 00ff h 0100 h 01ff h 0200 h 02ff h 0300 h 03ff h 0400 h 03bf h 03c0 h 04ff h 046f h 0470 h page4 not used (192bytes) (256bytes) (256bytes) (192bytes) (112bytes) system clock source select 000 : page0 001 : page1 initial value: 00 h address: 0df h rpr 010 : page2 011 : page3 - 76543210 - - r/w r/w r/w r/w rpr2 -- rpr1 rpr0 100 : page4
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 33 8.4 control registers address symbol register name r/w reset value addressing mode 76543210 00c0 p0 port0 data register r/w undefined byte,bit 00c1 p0io port0 i/o direction register w 00000000 byte 00c2 - reserved - - - 00c3 - reserved - - - 00c4 p2 port2 data register r/w undefined byte,bit 00c5 p2io port2 i/o direction register w 00000000 byte 00c6 p3 port3 data register r/w undefined byte,bit 00c7 - reserved - - - 00c8 p4 port4 data register r/w undefined byte,bit 00c9 - reserved - - - 00ca p5 port5 data register r/w undefined byte,bit 00cb - reserved - - - 00cc p6 port6 data register r/w undefined byte,bit 00cd - reserved - - - 00ce - reserved - - - 00cf - reserved - - - 00d0 t0cr timer0 mode control register r/w - - 000000 byte,bit 00d1 t0 timer0 register r 00000000 byte t0dr timer0 data register w 11111111 byte cdr0 timer0 capture data register r 0 0 000000 byte 00d2 t1cr timer1 mode control register r/w 00000000 byte,bit 00d3 t1dr timer1 data register w 11111111 byte t1ppr timer1 pwm period register w 11111111 byte 00d4 t1 timer1 register r 00000000 byte t1pdr timer1 pwm duty register r/w 00000000 byte,bit cdr1 timer1 capture data register r 0 0 000000 byte 00d5 pwm1hr timer1 pwm hi gh register w - - - - 0 0 0 0 byte 00d6 - reserved - - - 00d7 - reserved - - - 00d8 - reserved - - - 00d9 - reserved - - - 00da - reserved - - - 00db - reserved - - - 00dc sio3m sio3 mode control register r/w 0 - - 00000 byte,bit 00dd sio3r sio3 data shift register r/w undefined byte,bit table 8-1 control registers
hms81c2232/48 hms81c2332/48 34 feb. 2003 ver 1.00 preliminary 00de buz buzzer driver register w 11111111 byte 00df rpr ram page selection register r/w -----000 byte,bit 00e0 sio1m sio1 mode control register r/w 00000000 byte,bit 00e1 sio1r sio1 data shift register r/w undefined byte,bit 00e2 ienh interrupt enable register high r/w 00000000 byte,bit 00e3 ienl interrupt enable register low r/w 00000000 byte,bit 00e4 irqh interrupt request flag register high r/w 00000000 byte,bit 00e5 irql interrupt request flag register low r/w 00000000 byte,bit 00e6 ieds external interrupt edge selection register w 0 0 000000 byte,bit 00e7 rtcr remote timer control register r/w 00000000 byte,bit 00e8 rt remote timer register r 00000000 byte rtdr remote timer data register w 11111111 byte rtcp0 remote timer capture register0 r 00000000 byte 00e9 rtcp1 remote timer capture register1 r 00000000 byte 00ea adcm a/d converter mode register r/w - 0 000001 byte 00eb adr a/d converter data register r undefined byte 00ec bitr basic interval timer register r undefined byte ckctr clock control register w - 0010111 byte 00ed wdtr watchdog timer register r 00000000 byte w 01111111 byte 00ee - reserved - - - 00ef pfdr power fail detection register r/w -----100 byte 00f0 dspm0 display mode register0 r/w 00010000 byte,bit 00f1 dspm1 display mode register1 r/w 00000001 byte,bit 00f2 dspm2 display mode register2 r/w 00000000 byte,bit 00f3 - reserved - - - 00f4 psr port selection register w - - - 00000 byte 00f5 - reserved - - - 00f6 - reserved - - - 00f7 - reserved - - - 00f8 - reserved - - - 00f9 - reserved - - - 00fa scmr system clock mode register r/w - - - 00000 byte,bit 00fb smr sleep mode register w - ------0 byte 00fc pu0 pull-up resistor option register0 r/w 00000000 byte,bit 00fd - reserved - - - address symbol register name r/w reset value addressing mode 76543210 table 8-1 control registers
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 35 00fe pu2 pull-up resistor option register2 r/w 00000000 byte,bit 00ff stpc stop control register w 00000000 byte address symbol register name r/w reset value addressing mode 76543210 table 8-1 control registers registers are controlled by byte manipulation instru ction such as ldm etc., do not use bit manipulation w registers are controlled by both bit and byte manipulation instruction. r/w instruction such as set1, clr1 etc. if bit mani pulation instruction is used on these registers, content of other seven bits are may varied to unwanted value. - : this bit location is reserved.
hms81c2232/48 hms81c2332/48 36 feb. 2003 ver 1.00 preliminary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c0h p0 port0 data re gister (bit[7:0]) c1h p0io port0 direction register (bit[7:0]) c2h - reserved c3h - reserved c4h p2 port2 data re gister (bit[7:0]) c5h p2io port2 direction register (bit[7:0]) c6h p3 port3 data re gister (bit[7:0]) c7h - reserved c8h p4 port4 data re gister (bit[7:0]) c9h - reserved cah p5 port5 data re gister (bit[7:0]) cbh - reserved cch p6 port6 data register (bit[7:0]) cdh - reserved ceh - reserved cfh - reserved d0h t0cr - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st d1h t0/t0dr/ cdr0 timer0 register/timer0 data register capture0 data register d2h t1cr pol 16bit pwm1e cap1 t1ck1 t1ck0 t1cn t1st d3h t1dr t1ppr timer1 data register pwm1 period register d4h t1/cdr1 t1pdr timer1 register/capture1 data register pwm1 duty register d5h pwm1hr pwm1 high register (bit[3:0]) d6h - reserved d7h - reserved d8h - reserved d9h - reserved dah - reserved dbh - reserved dch sio3m pol iosw sm1 sm0 sck1 sck0 siost siosf ddh sio3r spi3 data register deh bur buck1 buck0 bur5 bur4 bur3 bur2 bur1 bur0 dfh rpr ram page selection register e0h sio1m pol iosw sm1 sm0 sck1 sck0 siost siosf table 8-2 control registers of hms81c2248 these registers of shaded area can not be access by bit manipulat ion instruction as " set1, clr1 ", but should be access by reg - ister operation instruction as " ldm dp,#imm ".
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 37 e1h sio1r spi1 data register e2h ienh int0e int1e t0e t1e e3h ienl ade wdte bite spie - - - - e4h irqh int0if int1if t0if t1if e5h irql adif wdtif bitif spiif - - - - e6h ieds ied1h ied1l ied0h ied0l e7h rtcr pol iosw sm1 sm0 sck1 sck0 siost siosf e8h rt/rtdr rtcp0 remotae timer register/remote timer data registor remote timer capture register0 e9h rtcp0 remote timer capture register1 eah adcm - aden ads3 ads2 ads1 ads0 adst adsf ebh adcr adc result data register ech bitr 1 basic interval timer data register ech ckctlr 1 - wakeup rcwdt wdton btcl bts2 bts1 bts0 edh wdtr wdtcl 7-bit watchdog counter register eeh - reserved efh pfdr 2 -----pfdispfdmpfds f0h dspm0 ied1h ied1l ied0h ied0l f1h dspm1 pol iosw sm1 sm0 sck1 sck0 siost siosf f2h dspm2 ied1h ied1l ied0h ied0l f3h - reserved f4h psr - - - - buzo ec0 int1 int0 f5h - reserved f6h - reserved f7h - reserved f8h - reserved f9h - reserved fahscmr ------cs1cs0 fbh - reserved fch pu0 pu07 pu06 pu05 pu04 pu03 pu02 pu01 pu00 fdh - reserved feh pu2 pu27 pu26 pu25 pu24 pu23 pu22 pu21 pu20 ffh stpc stop control register 1.the register bitr and ckctlr are located at same addr ess. address ech is read as bitr, written to ckctlr. 2.the register pfdr only be implemented on devices, not on in-circuit emulator. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 table 8-2 control registers of hms81c2248 these registers of shaded area can not be access by bit manipulat ion instruction as " set1, clr1 ", but should be access by reg - ister operation instruction as " ldm dp,#imm ".
hms81c2232/48 hms81c2332/48 38 feb. 2003 ver 1.00 preliminary 8.5 addressing mode the gms800 series mcu uses six addressing modes; ? register addressing ? immediate addressing ? direct page addressing ? absolute addressing ? indexed addressing ? register-indirect addressing (1) register addressing register addressing accesses the a, x, y, c and psw. (2) immediate addressing #imm in this mode, second byte (o perand) is accessed as a data immediately. example: 0435 adc #35h when g-flag is 1, then ram address is defined by 16-bit address which is composed of 8-bit ram paging register (rpr) and 8-bit immediate data. example: g=1 e45535 ldm 35h,#55h (3) direct page addressing dp in this mode, a address is sp ecified within direct page. example; g=0 c535 lda 35h ;a ram[35h] (4) absolute addressing !abs absolute addressing sets corresponding memory data to data, i.e. second byte (ope rand i) of command becomes lower level address and thir d byte (operand ii) becomes upper level address. with 3 bytes command, it is possible to access to whole memory area. adc, and, cmp, cmpx, cmpy, eor, lda, ldx, ldy, or, sbc, sta, stx, sty example; 0735f0 adc !0f035h ;a rom[0f035h] the operation within data memory (ram) asl, bit, dec, inc, lsr, rol, ror example; addressing accesses the address 0135 h regard- less of g-flag. 35 a+35h+c a 04 memory e4 0f100h data 55h ~ ~ ~ ~ data 0135h ? 35 0f102h 55 0f101h ? data 35 35h 0e551h data a ? ? ~ ~ ~ ~ c5 0e550h 07 0f100h ~ ~ ~ ~ data 0f035h ? f0 0f102h 35 0f101h ? a+data+c a address: 0f035
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 39 983501 inc !0135h ;a rom[135h] (5) indexed addressing x indexed direct page (no offset) {x} in this mode, a address is specified by the x register. adc, and, cmp, eor, lda, or, sbc, sta, xma example; x=15 h , g=1 d4 lda {x} ;acc ram[x]. x indexed direct page, auto increment {x}+ in this mode, a address is sp ecified within direct page by the x register and the content of x is increased by 1. lda, sta example; g=0, x=35 h db lda {x}+ x indexed direct page (8 bit offset) dp+x this address value is the second byte (operand) of com- mand plus the data of 9 -register. and it assigns the mem- ory in direct page. adc, and, cmp, eor, lda, ldy, or, sbc, sta sty, xma, asl, dec, inc, lsr, rol, ror example; g=0, x=0f5 h c645 lda 45h+x y indexed direct page (8 bit offset) dp+y this address value is the second byte (operand) of com- mand plus the data of y-register, which assigns memory in direct page. this is same with above (2). use y register instead of x. y indexed absolute !abs+y sets the value of 16-bit absolute address plus y-register data as memory.this addressi ng mode can specify memo- ry in whole area. example; y=55 h 98 0f100h ~ ~ ~ ~ data 135h ? 01 0f102h 35 0f101h ? data+1 data ? address: 0135 data d4 115h 0e550h data a ? ? ~ ~ ~ ~ data db 35h data ? a ? ? ~ ~ ~ ~ 36h ? x data 45 3ah 0e551h data a ? ? ~ ~ ~ ~ c6 0e550h 45h+0f5h=13ah ?
hms81c2232/48 hms81c2332/48 40 feb. 2003 ver 1.00 preliminary d500fa lda !0fa00h+y (6) indirect addressing direct page indirect [dp] assigns data address to us e for accomplishing command which sets memory data (or pair memory) by operand. also index can be used with index register x,y. jmp, call example; g=0 3f35 jmp [35h] x indexed indirect [dp+x] processes memory data as data, assigned by 16-bit pair memory which is determined by pair data [dp+x+1][dp+x] operand plus x-register data in direct page. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, x=10 h 1625 adc [25h+x] y indexed indirect [dp]+y processes memory data as data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by operand in di- rect page plus y-register data. adc, and, cmp, eor, lda, or, sbc, sta example; g=0, y=10 h 1725 adc [25h]+y absolute indirect [!abs] the program jumps to address specified by 16-bit absolute address. jmp example; g=0 d5 0f100h data a ? ~ ~ ~ ~ data 0fa55h 0fa00h+55h=0fa55h ? fa 0f102h 00 0f101h ? 0a 35h jump to ? ~ ~ ~ ~ 35 0fa00h e3 36h ? 3f 0e30ah next ~ ~ ~ ~ address 0e30ah 05 35h 0e005h ~ ~ ~ ~ 25 0fa00h e0 36h 16 0e005h data ~ ~ ~ ~ ? a + data + c a 25 + x(10) = 35 h ? ? 05 25h 0e005h + y(10) ? ~ ~ ~ ~ 25 0fa00h e0 26h ? 17 0e015h data ~ ~ ~ ~ ? = 0e015h a + data + c a
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 41 1f25e0 jmp [!0c025h] 25 0e025h jump to ~ ~ ~ ~ e0 0fa00h e7 0e026h ? 25 0e725h next ~ ~ ~ ~ 1f program memory ? address 0e30ah
hms81c2232/48 hms81c2332/48 42 feb. 2003 ver 1.00 preliminary 9. i/o ports the hms81c2232/48 has six ports (p0, p2, p3, p4, p5, and p6). these ports pins may be multiplexed with an alternate function for the peripheral features on the device. the hms81c2232/48 incorporates 16 output ports and 24 input/ output ports. every port is capable of 1-bit and 8-bit manipula- tions and can carry out consider ably varied control operations. besides port functions, the ports ca n also serve as built-in hard- ware input/ output pins. p0 and p2 port have data dir ection registers which can define these ports as output or input. a ?1? in the port direction register configure the corresponding port pi n as output. conversely, write ?0? to the corresponding bit to spec ify it as input pin. for exam- ple, to use the even numbered bit of p0 as output ports and the odd numbered bits as input ports, write ?55 h ? to address 0c1 h (p0 port direction register) during ini tial setting as shown in figure 9- 1. all the port direction register s in the hms81c2232/48 have 0 written to them by reset function. on the other hand, its initial sta- tus is input. figure 9-1 example of port i/o assignment 9.1 p0 and p0io register: p0 is an 8-bit high-voltage cmos bidirectional i/o port (address 0c0 h ). each port can be set individually as input and output through the p0io register (address 0c1 h ). when p00 through p07 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up resistor option register 0 (pu0). alternate functions in- clude external interrupt request input and timer input. reset in- put sets port 0 to input mode. p00~p01 ports are multiplexed with external interrupt input port(intp1, intp0), and p02 port is multiplexed with event counter input port (ec0). p0 3~p06 ports are multiplexed with analog input port and p07 port is multiplexed with buzzer out- put port(buzo). .the control register psr (address f4 h ) controls to select alter- nate function. after reset, this value is "0", port may be used as general i/o ports. to select a lternate function such as buzzer output, external event counter input and external interrupt in- put, write "1" to the corresponding bit of psr. regardless of the direction register p0io, psr is selected to use as alternate func- tions, port pin can be used as a corresponding al ternate features (buzo, ec0, int1, int0) port pin alternate function p00 p01 p02 p03 p04 p05 p06 p07 intp0 (external interrupt 0) intp1 (external interrupt 1) ti (timer input of remote control timer) an0 (analog input 0) an1 (analog input 1) an2 (analog input 2) an3 (analog input 3) buzo (buzzer driver output) i : input port write "55 h " to port r0 direction register 0 1 0 1 0 1 0 1 i o i o i o i o p0 data p2 data p0 direction p2 direction 0c0 h 0c1 h 0c4 h 0c5 h 76543210 bit 76543210 port o : output port p0 data register p0 address: 0c0 h reset value: undefined p07 p06 p05 p04 p03 p02 p01 p00 port direction p0 direction register p0io address : 0c1 h reset value : 00 h 0: input 1: output input / output data port selection register psr address : 0f4 h reset value : ---0 0000 b 0: p00 1: intp0 0 0: p01 1: intp1 0: p07 1: buzo 0: p64 1: pwm1 1 2 3 4 - - - 0: p63 1: ec0 p0 pull-up resistor pu0 address: 0fc h reset value: 00 h selection register 0: disable 1: enable pull-up resister selection
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 43 9.2 p2 and p2io register: p2 is an 8-bit high-voltage cmos bidirectional i/o port (address 0c4 h ). each port can be set indi vidually as input and output through the p2io register (address 0c5 h ). when p20 to p27 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up re- sistor option register 2 (pu2). alternate functions include serial interface data input/output a nd clock input/out put. reset input sets port 2 to input mode. p20 to p21 port is multiplexed w ith serial interface3 data input/ output(so3), clock input/output(sck3). p22~p24 ports are mul- tiplexed with analog input port (ani4~ani6). p25~p27 port is multiplexed with serial inte rface1 data input (si1)/output(so1), clock input/output(sck1). 9.3 p3 register: p3 is an 8-bit output only port(address 0c6 h ). on-chip pull-down resistors can be connected in 1- bit units with the mask option in case of mask rom model. the hms87c2232/48 has no pull- down resistor. in a ddition, fip controller /driver segment/digit output is provided as an alternate function. on-chip pull-down resistors can be connected in 1-bit units with the mask option. pull -down resistor to v disp or v ss0 can be se- lected in 1-bit units. the hms87c2232/48 has no pull-down re- sistor. in addition, fip controll er/driver output is provided as an alternate function. 9.4 p4 register: p4 is an 8-bit output only port(address 0c8 h ). on-chip pull-down resistors can be connected in 1- bit units with the mask option in case of mask rom model. the hms87c2232/48 has no pull- down resistor. in a ddition, fip controller /driver segment/digit output is provided as an alternate function. on-chip pull-down resistors can be connected in 1-bit units with the mask option. pull -down resistor to v disp or v ss0 can be se- lected in 1-bit units. the hms87c2232/48 has no pull-down re- sistor. in addition, fip controll er/driver output is provided as an alternate function. 9.5 p5 register: p5 is an 8-bit bidirectional i/o port (address 0ca h ). port 5 is an 8-bit input/output port with output latch. when using this port as an output port, the value assigned to the output latch (p50 through p57) is output. when it is used as an input port, set the output latch (p50 through p57) to ?0?, and read the port level read (p50 port pin alternate function p20 p21 p22 p23 p24 p25 p26 p27 sck3 (serial3 clock input/output) so3 (serial3 data output) an4 (analog input 4) an5 (analog input 5) an6 (analog input 6) so1 (serial1 data output) si1 (serial1data input) sck1 (serial1 clock input/output) p2 data register p2 address: 0c4 h reset value: undefined p27 p26 p25 p24 p23 p22 p21 p20 port direction p2 direction register p2io address : 0c5 h reset value : 00 h 0: input 1: output input / output data p2 pull-up resistor pu2 address: 0fc h reset value: 00 h selection register 0: disable 1: enable pull-up resister selection port pin alter nate function p30~p37 fip24-fip31 port pin alternate function p40~p47 fip32-fip39 p3 data register p3 address: 0c6 h reset value: undefined p37 p36 p35 p34 p33 p32 p31 p30 output data p4 data register p4 address: 0c8 h reset value: undefined p47 p46 p45 p44 p43 p42 p41 p40 output data
hms81c2232/48 hms81c2332/48 44 feb. 2003 ver 1.00 preliminary through p57). on-chip pull-down resistors can be connected in 1-bit units with the mask option. pull -down resistor to v disp or v ss0 can be se- lected in 1-bit units. the hm s87c2232/48 has no pull-down re- sistor. in addition, fip controll er/driver output is provided as an alternate function. reset input sets port 5 to input mode. 9.6 p6 register: p6 is an 5-bit bidirect ional i/o port (address 0cc h ). port 64 is multiplexed with pulse width modulator (pwm). port 6 is an 5-bit input/output port with output latch. when using this port as an output port, the value assigned to the output latch (p60 through p64) is output. when it is used as an input port, set the output latch (p60 through p64) to ?0?, and read the port level read (p60 through p64). on-chip pull-down resistors can be connected in 1-bit units with the mask option. pull -down resistor to v disp or v ss0 can be se- lected in 1-bit units. the hms87c2232/48 has no pull-down re- sistor. in addition, fip controll er/driver output is provided as an alternate function. re set input sets port 6 to input mode. port pin alternate function p50~p57 fip40-fip47 port pin alternate function p60 p61 p62 p63 p64 fip48 fip49 fip50 fip51 / ec0 fip52 / pwm1o p5 data register p5 address: 0ca h reset value: undefined p57 p56 p55 p54 p53 p52 p51 p50 input / output data p6 data register p6 address: 0cc h reset value: undefined r67 r66 r65 r64 r63 r62 r61 r60 input / output data port selection register psr address : 0f4 h reset value : ---0 0000 b 0: p00 1: intp0 0 0: p01 1: intp1 0: p07 1: buzo 0: p64 1: pwm1 1 2 3 4 - - - 0: p63 1: ec0
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 45 10. clock generator as shown in figure 10-1, the cl ock generator produces the basic clock pulses which provide the syst em clock to be supplied to the cpu and the peripheral hardware. the clock generator pro- duces the basic clock pulses which provide the system clock to be supplied to the cpu and peripheral hardware. the main system clock oscillator oscillates with a crystal resona- tor or a ceramic resonator connected to the xin and xout pins. external clocks can be input to the main system clock os- cillator. in this case, input a clock signal to the xin pin and open the xout pin the system clock can also be obtained from the external oscillator. . figure 10-1 block diagram of clock generator the clock generator produces th e system clocks forming clock pulse, which are supplied to the cpu and the peripheral hard- ware. the internal system clock can be selected by bit1, and bit0 of the system clock mode register(scmr). the register is shown in figure 10-2. to the peripheral block, the cl ock among the not-divided original clocks, divided by 2 , 4,..., up to 4096 can be provided. peripheral clock is enabled or disabled by st op instruction. on the initial reset, internal system clock is ps1 which is the fastest and other clock can be provided by bit1 and bit0 of scmr. figure 10-2 system clock control register internal system clock (cpu clock) x out pin prescaler x in pin 1 peripheral clock mux 2 4 8 16 128 256 512 1024 32 64 2 8 16 64 system clock mode register cs1 ps0 ps1 ps2 ps3 ps4 ps5 ps6 ps7 ps8 ps9 ps10 clock pulse f ex (mhz) ps0 ps3 ps2 ps4 ps1 ps10 ps9 ps5 ps6 ps7 4 frequency period 4m 1m 500k 250k 2m 125k 62.5k 250n 500n 1u 2u 4u 8u 16u 32u 64u 256u 128u 3.906k 7.183k 15.63k 31.25k ps8 f ex generator oscillation circuit 2048 4096 ps11 ps12 cs0 scmr select clock ps12 ps11 1024u 512u 976.6 1.953k system clock source select 00: x in 2 01: x in 8 initial value: 00 h address: 0fa h scmr 10: x in 16 11: x in 64 - 76543210 - - r/w r/w r/w r/w - -- cs1 cs0
hms81c2232/48 hms81c2332/48 46 feb. 2003 ver 1.00 preliminary 11. basic interval timer the hms81c2232/48 has one 8-bit basic interval timer that is free-run, can not stop. block diag ram is shown in figure 11-1. in addition, the basic interval timer generates the time base for watchdog timer counting. it also provides a basic interval timer interrupt (bitif). the 8-bit basic interval timer regi ster (bitr) is increased every internal count pulse which is di vided by prescaler. since prescal- er has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. as the count overflows from ff h to 00 h , this overflow causes to generate the basic interval timer in- terrupt. the bitif is interrupt reque st flag of basic interval tim- er. the basic interval timer is controlled by the clock control register (ckctlr) shown in figure 11-2. when write "1" to bit btcl of ckctlr, bitr register is cleared to "0" and restart to c ount-up. the bit btcl becomes "0" after one machine cycle by hardware. if the stop instruction executed after writing "1" to bit wake- up of ckctlr, it goes into the wake-up timer mode. in this mode, all of the block is halted except the oscillator, prescaler (only fxin 2048) and timer0. if the stop instruction executed after writing "1" to bit rcwdt of ckctlr, it goes into the in ternal rc oscilla ted watchdog tim- er mode. in this mode, all of the block is halted except the internal rc oscillator, basic interval timer and watchdog timer. more detail informations are explaine d in power saving function. the bit wdton decides watchdog time r or the normal 7-bit timer. source clock can be selected by lower 3 bits of ckctlr. bitr and ckctlr are located at sa me address, and address 0ec h is read as a bitr, and written to ckctlr. figure 11-1 block diagram of basic interval timer mux basic interval bitr select input clock 3 basic interval timer source clock 8-bit up-counter bts[2:0] btcl 1024 512 256 128 64 32 16 8 to watchdog timer (wdtck) ckctlr clear overflow internal bus line clock control register [0ec h ] [0ec h ] bitif read x in pin prescaler timer interrupt internal rc osc rcwdt 1 0 wakeup stop
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 47 table 11-1 basic interval timer interrupt time figure 11-2 bitr: basic in terval timer mode register example 1: basic interval timer interrupt request flag is generated every 4.096ms at 4mhz. : ldm ckctlr,#03h set1 bite ei : example 2: basic interval timer interrupt request flag is generated every 1.024ms at 4mhz. : ldm ckctlr,#01h set1 bite ei : ckctlr [2:0] source clock interrupt (overflow) period (ms) @ f xin = 4mhz 000 001 010 011 100 101 110 111 ps3(f xin 8) ps4(f xin 16) ps5(f xin 32) ps6(f xin 64) ps7(f xin 128) ps8(f xin 256) ps9(f xin 512) ps10(f xin 1024) 0.512 1.024 2.048 4.096 8.192 16.384 32.768 65.536 btcl 76543210 rcwdt - bts1 basic interval timer source clock select 000: f xin 8 001: f xin 16 010: f xin 32 011: f xin 64 100: f xin 128 101: f xin 256 110: f xin 512 111: f xin 1024 basic interval timer clear bit 0: normal operation (free-run) 1: clear 8-bit counter (bitr) to ?0?. this bit becomes 0 automatically initial value: --01 0111 b address: 0ec h after one machine cycle, and starts counting. ckctlr initial value: undefined address: 0ec h bitr both register are in same address, when write, to be a ckctlr, when read, to be a bitr. caution: 8-bit free-run binary counter wdton bts0 bts2 btcl btcl 76543210 0: operate as a 7-bit general timer 1: enable watchdog timer operation see the section ?watchdog timer?. 0: disable internal rc watchdog timer 1: enable internal rc watchdog timer - watchdog timer enable bit rc watchdog selection bit
hms81c2232/48 hms81c2332/48 48 feb. 2003 ver 1.00 preliminary 12. watchdog timer the watchdog timer rapidly dete cts the cpu malfunction such as endless looping caused by noise or the like, and resumes the cpu to the normal state. the watchdog timer signal for de tecting malfunction can be se- lected either a reset cpu or a interrupt request. when the watchdog timer is not being used for malfunction de- tection, it can be used as a timer to generate an interrupt at fixed intervals. the purpose of the watc hdog timer is to detect the mal- function (runaway) of program due to external noise or other causes and return the opera tion to the normal condition. the watchdog timer has two types of clock source. the first type is an on-chip rc oscillator which does not require any external components. this rc oscillator is separate from the external oscillator of the xin pi n. it means that the watchdog tim- er will run, even if the clock on the xin pin of the device has been stopped, for example, by entering the stop mode. the other type is a prescaled system clock. the watchdog timer consists of 7-bit binary counter and the watchdog timer data register. wh en the value of 7-bit binary counter is equal to the lower 7 bits of wdtr, the interrupt re- quest flag is generated. this can be used as wdt interrupt or re- set the cpu in accordance with the bit wdton. note: because the watchdog timer counter is enabled af- ter clearing basic interval ti mer, after the bit wdton set to "1", maximum error of timer is depend on prescaler ratio of basic interval timer. the 7-bit binary counter is cleared by setting wdtcl(bit7 of wdtr) and the wdtcl is cleared automatically after 1 machine cycle. the rc oscillated watchdog timer is activated by setting the bit rcwdt as shown below. ldm ckctlr,#3fh; enable the rc-osc wdt ldm wdtr,#0ffh; set the wdt period stop ; enter the stop mode nop nop ; rc-osc wdt running : the rcwdt oscillation period is vary with temperature, vdd and process variations from pa rt to part (approximately, 40~120us). the following equati on shows the rcwdt oscillat- ed watchdog timer time-out. t rcwdt =clk rcwdt 2 8 [ wdtr.6~0]+(clk rcwdt 2 8 )/2 where, clk rcwdt = 40~120us in addition, this watchdog timer can be used as a simple 7-bit tim- er by interrupt wdtif. the interval of watchdog timer interrupt is decided by basic inte rval timer. interval equation is as below. t wdt = [wdtr.6~0] interval of bit figure 12-1 block diagram of watchdog timer to reset cpu basic interval timer count enable watchdog 7-bit compare data comparator watchdog timer interrupt clear clear wdtif counter (7-bit) wdtcl ?0? ?1? wdton in ckctlr [0ec h ] overflow watchdog timer register wdtr internal bus line 7 [0ed h ] source
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 49 watchdog timer control figure 12-2 shows the watchdog timer control register. the watchdog timer is automatica lly disabled after reset. the cpu malfunction is detected during setting of the detection time, selecting of output, and cl earing of the binary counter. clearing the binary counter is repe ated within the detection time. if the malfunction occurs for any cause, the watchdog timer out- put will become active at the rising overflow from the binary counters unless the binary counter is cleared. at this time, when wdton=1, a reset is generate d, which drives the reset pin to low to reset the internal hard ware. when wdton=0, a watchdog timer interrupt (wdt if) is generated. the watchdog timer temporarily stops counting in the stop mode, and when the stop mode is released, it automatically re- starts (continues counting). figure 12-2 wdtr: watchdog timer data register example: sets the watc hdog timer detection time to 0.5 sec at 4.19mhz 76543210 clear count flag 0: free-run count initial value: 0111_1111 b address: 0ed h wdtr ww ww 1: when the wdtcl is set to "1", binary counter is cleared to ?0?. and the wdtcl becomes ?0? automatically after one machine cycle. counter count up again. 7-bit compare data wwww note: the wdton bit is in register ckctlr. wdtcl ldm ckctlr,#3fh ; select 1/2048 clock source , wdton 1, clear counter ldm wdtr,#04fh ldm wdtr,#04fh ; clear counter : : : : ldm wdtr,#04fh ; clear counter : : : : ldm wdtr,#04fh ; clear counter within wdt detection time within wdt detection time
hms81c2232/48 hms81c2332/48 50 feb. 2003 ver 1.00 preliminary enable and disable watchdog watchdog timer is enabled by setting wdton (bit 4 in ckctlr) to ?1?. wdton is initialized to ?0? during reset and it should be set to ?1? to ope rate after reset is released. example: enables wa tchdog timer for reset : ldm ckctlr,#xx1x_xxxxb; wdton 1 : : the watchdog timer is disabled by clearing bit 5 (wdton) of ckctlr. the watchdog timer is ha lted in stop mode and re- starts automatically after stop mode is released. watchdog timer interrupt the watchdog timer can be also us ed as a simple 7-bit timer by clearing bit5 of ckctlr to ?0 ?. the interval of watchdog timer interrupt is decided by basic inte rval timer. interval equation is shown as below. the stack pointer (sp) should be initialized before using the watchdog timer output as an interrupt source. example: 7-bit timer interrupt set up. ldm ckctlr,#xx0xxxxxb; wdton 0 ldm wdtr,#7fh ; wdtcl 1 : figure 12-3 watchdog timer timing if the watchdog timer output becomes active, a reset is generated, which drives the reset pin low to reset the internal hardware. the main clock oscilla tor also turns on when a watchdog timer re- set is generated in sub clock mode. t wdtr interval of bit = 2 3 n source clock binary-counter wdtr wdtif interrupt wdtr "0100_0011 b " 1 0 match detect counter clear 1 2 30 bit overflow 3 wdt reset reset
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 51 13. timer/event counter the hms81c2232/48 has two timer/counter registers. each module can generate an interrupt to indicate that an event has oc- curred (i.e. timer match). timer 0 and timer 1 are can be used either two 8-bit timer/ counter or one 16-bit timer/ counter with combine them. in the "timer" function, the regi ster is increased every internal clock input. thus, one can think of it as counting internal clock input. since a leas t clock consists of 2 a nd most clock consists of 2048 oscillator periods, the count ra te is 1/2 to 1/2048 of the os- cillator frequency in timer0. and timer1 can use the same clock source too. in addition, timer1 has more fast clock source (1/1 to 1/8). in the ?counter? function, the regi ster is increased in response to a 1-to-0 (falling edge) or 0-to-1 (rising edge) transition at its cor- responding external input pin, ec0. in addition the ?capture? function, the register is increased in re- sponse external or internal clock sources same with timer or counter function. when external clock edge input , the count reg- ister is captured into capture data register cdrx. timer1 is shared with "pwm " function and "compare output" function it has seven operating modes: "8-bit timer/counter", "16-bit tim- er/counter", "8-bit capture", "16-bit capture", "8-bit compare out- put", "16-bit compare output" and "10-bit pwm" which are selected by bit in timer mode re gister tm0 a nd tm1 as shown in figure 13-1 and table 13-1. 16bit cap0 cap1 pwm1e t0ck [2:0] t1ck [1:0] pwm1o timer 0 timer 1 0 0 0 0 xxx xx 0 8-bit timer 8-bit timer 0 0 1 0 111 xx 0 8-bit event counter 8-bit capture 0 1 0 0 xxx xx 1 8-bit capture (internal clock) 8-bit compare output 0 x 0 1 xxx xx 1 8-bit timer/counter 10-bit pwm 1 0 0 0 xxx 11 0 16-bit timer 1 0 0 0 111 11 0 16-bit event counter 1 1 x 0 xxx 11 0 16-bit capture (internal clock) 1 0 0 0 xxx 11 1 16-bit compare output table 13-1 operating modes of timer0 and timer1
hms81c2232/48 hms81c2332/48 52 feb. 2003 ver 1.00 preliminary figure 13-1 tm0, tm1 registers btcl 76543210 16bit pol t1cn initial value: 00 h address: 0d2 h t1cr t1st t1ck0 t1ck1 pwm1e cap1 bit name bit position description pol tm1.7 0: pwm duty active low 1: pwm duty active high 16bit tm1.6 0: 8-bit mode 1: 16-bit mode pwmie tm1.5 0: disable pwm 1: enable pwm cap1 tm1.4 0: timer/counter mode 1: capture mode selection flag t1ck1 t1ck0 tm1.3 tm1.2 00: 8-bit timer, clock source is f xin 01: 8-bit timer, clock source is f xin 2 10: 8-bit timer, clock source is f xin 8 11: 8-bit timer, clock source is using the the timer 0 clock t0cn tm1.1 0: stop the timer 1: a logic 1 starts the timer. t0st tm1.0 0: when cleared, stop the counting. 1: when set, timer 0 count register is cleared and start again. btcl 543210 - - t0cn initial value: --000000 b address: 0d0 h t0cr t0st t0ck0 t0ck1 cap0 t0ck2 bit name bit position description cap0 tm0.5 0: timer/counter mode 1: capture mode selection flag t0ck2 t0ck1 t0ck0 tm0.4 tm0.3 tm0.2 000: 8-bit timer, clock source is f xin 2 001: 8-bit timer, clock source is f xin 4 010: 8-bit timer, clock source is f xin 8 011: 8-bit timer, clock source is f xin 32 100: 8-bit timer, clock source is f xin 128 101: 8-bit timer, clock source is f xin 512 110: 8-bit timer, clock source is f xin 2048 111: ec0 (external clock) t0cn tm0.1 0: stop the timer 1: a logic 1 starts the timer. t0st tm0.0 0: when cleared, stop the counting. 1: when set, timer 0 count register is cleared and start again. 76543210 initial value: undefined address: 0d1 h t0dr read: count value read write: compare data write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 76543210 initial value: undefined address: 0d3 h t1dr r/w r/w r/w r/w r/w r/w r/w r/w
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 53 13.1 8-bit timer / counter mode the hms81c2232/48 has two 8-bit timer/counters, timer 0, timer 1 as shown in figure 13-2. the "timer" or "counter" function is selected by mode registers tmx as shown in figure 13-1 and ta ble 13-1. to use as an 8-bit timer/counter mode, b it cap0 of t0cr is cleared to "0" and bits 16bit of t1cr should be cleared to ?0?(table 13-1). figure 13-2 8-bit timer/counter 0, 1 ec0 pin 2 4 8 xin pin mux prescaler clear 0: stop 1: clear and start t0st t0ck[2:0] 111 000 001 010 t0cn mux t1if clear 0: stop 1: clear and start t1st t1ck[1:0] 11 00 01 timer 1 interrupt 1 2 8 tdr0 (8-bit) tdr1 (8-bit) t1 (8-bit) t0 (8-bit) comparator comparator timer 0 timer 1 btcl 76543210 - -t0cn initial value: --000000 b address: 0d0 h t0cr t0st t0ck0 t0ck1 cap0 t0ck2 -- xx x x x means don?t care 32 128 512 2048 011 100 101 110 t0if timer 0 interrupt t1cn 10 initial value: 00 h address: 0d2 h t1cr x means don?t care 0 x btcl 76543210 16bit pol t1cn t1st t1ck0 t1ck1 pwm1e cap1 x0 x x x x 00 edge detector p64/pwm1o f/f
hms81c2232/48 hms81c2332/48 54 feb. 2003 ver 1.00 preliminary example 1: timer0 = 2ms 8-bit timer mode at 4mhz timer1 = 0.5ms 8-bit timer mode at 4mhz ldm tdr0,#249 ldm tdr1,#249 ldm t0cr,#0000_1111b ldm t1cr,#0000_1011b set1 t0e set1 t1e ei example 2: timer0 = 8-bit event counter mode timer1 = 0.5ms 8-bit timer mode at 4mhz ldm tdr0,#249 ldm tdr1,#249 ldm t0cr,#0001_1111b ldm t1cr,#0000_1011b set1 t0e set1 t1e ei note: the contents of timer data register tdrx should be initialized 1 h ~ff h , not 0 h , because it is undefined after re- set. these timers have each 8-bit count register and data register. the count register is incr eased by every internal or external clock in- put. the internal clock has a prescal er divide ratio option of 2, 4, 8, 32,128, 512, 2048 selected by control bits t0ck[2:0] of regis- ter (t0cr) and 1, 2, 8 selected by control bits t1ck[1:0] of reg- ister (t1cr). in the timer 0, time r register t0 increases from 00 h until it matches t0dr and then reset to 00 h . the match output of timer 0 generates timer 0 interrupt (latched in t0if bit). as tdrx and tx register are in same address, when reading it as a tx, written to tdrx. in counter function, the counter is increased every 0-to-1(1-to-0) (rising & falling edge) transition of ec0 pin. in order to use counter function, the bit ec0 of the port selection regis- ter(psr.3) is set to "1". the time r 0 can be used as a counter by pin ec0 input, but timer 1 can not.
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 55 8-bit timer mode in the timer mode, the internal clock is used for counting up. thus, you can think of it as counting internal clock input. the contents of tdr n are compared with the contents of up-counter, t n . if match is found, a timer 1 inte rrupt (t1if) is generated and the up-counter is cleared to 0. counting up is resumed after the up-counter is cleared. as the value of tdr n is changeable by software, time interval is set as you want figure 13-3 timer mode timing chart figure 13-4 timer count example 0 n-2 2 0 n 3 n-1 n source clock up-counter tdr1 t1if interrupt start count 1 23 1 4 match detect counter clear ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ timer 1 (t1if) interrupt tdr1 time occur interrupt occur interrupt occur interrupt interrupt period up-count ~ ~ ~ ~ 0 1 2 3 4 5 6 7a 7c count pulse = 8 s x (124+1) 7b match example: make 2ms interrupt using by timer0 at 4mhz ldm t0cr,#0fh ; divide by 32 ldm tdr0,#124 ; 8us x (124+1)= 1ms set1 t0e ; enable timer 0 interrupt ei ; enable master interrupt period when tdr0 = 124 d = 7c h f xin = 4 mhz interrupt period = 4 10 6 hz 1 32 (124+1) = 1 ms tm0 = 0000 1111 b (8-bit timer mode, prescaler divide ratio = 32) 8 s (tdr0 = t0) 7c 0
hms81c2232/48 hms81c2332/48 56 feb. 2003 ver 1.00 preliminary 8-bit event counter mode in this mode, counting up is star ted by an external trigger. this trigger means falling edge or ri sing edge of the ec0 pin input. source clock is used as an intern al clock selected with timer mode register t0cr. the contents of timer data register t0dr is com- pared with the contents of the up-counter t0. if a match is found, an timer interrupt request flag t0 if is generated, and the counter is cleared to ?0?. the counter is restart and count up continuously by every falling edge or rising edge of the ec0 pin input. the maximum frequency applied to the ec0 pin is f xin /2 [hz]. in order to use event counter func tion, the bit 3 of theport selec- tion register(psr.3) is required to be set to ?1?. after reset, the value of timer da ta register t0dr is undefined, it should be initiali zed to between 0 h ~fe h not to "0"the interval period of timer is calcul ated as below equation. figure 13-5 event counter mode timing chart figure 13-6 count operation of timer / event counter period (sec) 1 f xin ---------- - 2 divide (tdr0+1) = 0 1 2 1 0 n 2 ~ ~ ~ ~ ~ ~ n-1 n ~ ~ ~ ~ ~ ~ ec n pin input up-counter tdr1 t1if interrupt start count timer 1 (t1if) interrupt tdr1 time occur interrupt occur interrupt stop clear & start disable enable start & stop t1st t1cn control count u p- c o un t ~ ~ ~ ~ t1st = 0 t1st = 1 t1cn = 0 t1cn = 1
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 57 13.2 16-bit timer / counter mode the timer register is being run with 16 bits. a 16-bit timer/coun- ter register t0, t1 are increased from 0000 h until it matches t0dr, t1dr and then resets to 0000 h . the match output gener- ates timer 0 interrupt not timer 1 interrupt. the clock source of the timer 0 is selected either internal or ex- ternal clock by bit t0ck[2:0]. in 16-bit mode, the bits t1ck[1:0] and 16bit of t1cr should be set to "1" respectively. figure 13-7 16-bit timer/counter 13.3 8-bit capture mode the timer 0 capture mode is set by bit cap0 of timer mode reg- ister tcr1 (bit cap1 of timer mode register t1ce for timer 1) as shown in figure 13-8. as mentioned above, not only ti mer 0 but timer 1 can also be used as a capture mode. the timer/counter register is in creased in response internal or external input. this counting func tion is same with normal timer mode, and timer interrupt is generated when timer register t0 (t1) increases and ma tches tdr0 (tdr1). this timer interrupt in capture m ode is very useful when the pulse width of captured signal is more wider than the maximum period of timer. for example, in figure 13-10, th e pulse width of captured signal is wider than the timer data value (ff h ) over 2 times. when ex- ternal interrupt is occurre d, the captured value (13 h ) is more little than wanted value. it can be obtained correct value by counting clear 0: stop 1: clear and start t0st t0cn t1dr + t0dr comparator timer 0 + timer 1 timer 0 (16-bit) higher byte lower byte (16-bit) compare data t1 + t0 (16-bit) 1 0 (not timer 1 interrupt) edge btcl 76543210 - -t0cn initial value: --000000 b address: 0d0 h t0cr t0st t0ck0 t0ck1 cap0 t0ck2 -- xx x x x means don?t care initial value: 00 h address: 0d2 h t1cr x means don?t care 0x btcl 76543210 16bit pol t1cn t1st t1ck0 t1ck1 pwm1e cap1 x1 x x 1 1 00 ec0 pin 2 4 8 xin pin mux prescaler t0ck[2:0] 111 000 001 010 32 128 512 2048 011 100 101 110 detector t0if timer 0 interrupt
hms81c2232/48 hms81c2332/48 58 feb. 2003 ver 1.00 preliminary the number of timer overflow occurrence. timer/counter still does the above , but with the added feature that a edge transition at external input intx pin causes the current value in the timer x register (t0,t1 ), to be captured into registers cdrx (cdr0, cdr1), respectivel y. after captured, timer x reg- ister is cleared and re starts by hardware. note: the cdrx, tdrx and tx are in same address. in the capture mode, reading oper ation is read the cdrx, not tx because path is opened to the cdrx, and tdrx is only for writing operation. it has three transition modes: "fal ling edge", "rising edge", "both edge" which are selected by in terrupt edge selection register ieds (refer to external interrupt section). in addition, the transi- tion at intx pin gene rate an interrupt.
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 59 figure 13-8 8-bit capture mode int0if 0: stop 1: clear and start t0st int0 interrupt t0cn cdr0 (8-bit) t0 (8-bit) ?01? ?10? ?11? capture ieds[1:0] ec0 pin 2 4 8 xin pin mux prescaler t0ck[2:0] 111 000 001 010 mux t1ck[1:0] 11 00 01 1 2 8 32 128 512 2048 011 100 101 110 10 int0 pin int1if 0: stop 1: clear and start t1st int1 interrupt t1cn cdr1 (8-bit) t1 (8-bit) ?01? ?10? ?11? capture ieds[1:0] int1 pin btcl 76543210 - -t0cn initial value: --000000 b address: 0d0 h t0cr t0st t0ck0 t0ck1 cap0 t0ck2 -- xx x x x means don?t care initial value: 00 h address: 0d2 h t1cr x means don?t care 1 x btcl 76543210 16bit pol t1cn t1st t1ck0 t1ck1 pwm1e cap1 x0 x x x x 01 edge detector clear clear
hms81c2232/48 hms81c2332/48 60 feb. 2003 ver 1.00 preliminary figure 13-9 input capture operation figure 13-10 excess timer overflow in capture mode ~ ~ ext. int0 pin interrupt request t0 time up-count ~ ~ ~ ~ 0 1 2 3 4 5 6 7 8 9 n n-1 capture ( timer stop ) clear & start interrupt interval period delay ( int0f ) ext. int0 pin interrupt request ( int0f ) this value is loaded to cdr0 20ns 5ns interrupt interval period=01 h +ff h +01 h +ff h +01 h +13 h =214 h ff h ff h ext. int0 pin interrupt request ( int0f ) 00 h 00 h interrupt request ( t0f ) t0 13 h
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 61 13.4 16-bit capture mode 16-bit capture mode is the same as 8-bit capture, except that the timer register is be ing run will 16 bits. the clock source of the timer 0 is selected either internal or ex- ternal clock by bit t0ck2, t0ck1 and t0ck0. in 16-bit mode, the bits t1ck1,t1ck0 and 16bit of t1cr should be set to "1" respectively. figure 13-11 16-bit capture mode 0: stop 1: clear and start t0st t0cn capture cdr1 + cdr0 higher byte lower byte (16-bit) capture data tdr1 + tdr0 (16-bit) int0if int0 interrupt ?01? ?10? ?11? ieds[1:0] ec0 pin 2 4 8 xin pin mux prescaler t0ck[2:0] 111 000 001 010 32 128 512 2048 011 100 101 110 int0 pin btcl 76543210 - -t0cn initial value: --000000 b address: 0d0 h t0cr t0st t0ck0 t0ck1 cap0 t0ck2 -- xx x x x means don?t care initial value: 00 h address: 0d2 h t1cr x means don?t care 1 x btcl 76543210 16bit pol t1cn t1st t1ck0 t1ck1 pwm1e cap1 x1 x x 1 1 0x edge detector clear
hms81c2232/48 hms81c2332/48 62 feb. 2003 ver 1.00 preliminary example 1: timer0 = 16-bit time r mode, 0.5s at 4mhz ldm t0cr,#0000_1111b;8us ldm t1cr,#0 1 00_ 11 00b;16bit mode ldm tdr0,#<62499 ;8us x 62500 ldm tdr1,#>62499 ;=0.5s set1 t0e ei : : example 2: timer0 = 16-bit event counter mode ldm psr,#0000_ 1 000b;ec0 set ldm t0cr,#000 1 _ 11 11b;countermode ldm t1cr,#0 1 00_ 11 00b;16bit mode ldm tdr0,#<0ffh ; ldm tdr1,#>0ffh ; set1 t0e ei : : example 3: timer0 = 16-bit capture mode ldm psr,#0000_000 1 b;int0 set ldm tm0,#00 1 0_1111b;capture mode ldm tm1,#0 1 00_ 11 00b;16bit mode ldm tdr0,#<0ffh ; ldm tdr1,#>0ffh ; ldm ieds,#01h;falling edge set1 t0e ei : : 13.5 pwm mode the hms81c2232/48 has a high sp eed pwm (pulse width mod- ulation) functions which shared with timer1. in pwm mode, pin r64/pwm1o outputs up to a 10-bit resolu- tion pwm output. this pin should be configured as a pwm out- put by setting "1" bit pwm1o in psr.4 register. the period of the pwm output is determined by the t1ppr (pwm1 period register) and pwm1hr[3:2] (bit3,2 of pwm1 high register) and the duty of th e pwm output is determined by the t1pdr (pwm1 duty registe r) and pwm1hr[1:0] (bit1,0 of pwm1 high register). the user writes the lower 8-bit period value to the t1ppr and the higher 2-bit period value to the pwm1hr[3:2]. and writes duty value to the t1pdr and the pwm1hr[1:0] same way. the t1pdr is configured as a double buffering for glitchless pwm output. in figure 13-12, the duty data is transferred from the master to the slave when the period data matche d to the count- ed value. (i.e. at the be ginning of next duty cycle) pwm period = [pwm1hr[3:2]t1ppr] x source clock pwm duty = [pwm1hr[1:0]t1pdr] x source clock the relation of frequency and reso lution is in inverse proportion. table 13-2 shows the relation of pwm frequency vs. resolution. if it needed more higher frequency of pwm, it should be reduced resolution. the bit pol of t1cr decides the polarity of duty cycle. if the duty value is set same to the period value, the pwm output is determined by the bit pol (1: high, 0: low). and if the duty value is set to "00 h ", the pwm output is determined by the bit pol (1: low, 0: high). it can be changed duty value wh en the pwm output. however the changed duty value is output after the current period is over. and it can be maintained the duty value at present output when changed only period value shown as figure 13-14. as it were, the absolute duty time is not change d in varying frequency. but the changed period value must greater than the duty value. note: if changing the timer1 to pwm function, it should be stop the timer clock firstly, and then set period and duty reg- ister value. if user writes register vlaues while timer is in op- eration, these register could be set with certain values. ex) sample program @4mhz 2us resolution frequency t1ck[1:0] = 00(250ns) t1ck[1:0] = 01(500ns) t1ck[1:0] = 10(2us) 10-bit 3.9khz 0.98khz 0.49khz 9-bit 7.8khz 1.95khz 0.97khz 8-bit 15.6khz 3.90khz 1.95khz 7-bit 31.2khz 7.81khz 3.90khz table 13-2 pwm frequency vs. resolution at 4mhz
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 63 ldm t1cr,#1010_1010b; set clock & pwm1e ldm t1ppr,#199 ; period :400us=2usx(199+1) ldm t1pdr,#99 ; duty:200us=2usx(99+1) ldm pwm1hr,00h ldm t1cr,#1010_1011b ; start timer1 13.6 8-bit compare output (16-bit) the hms81c2232/48 has a function of timer compare output. to pulse out, the timer match can goes to port pin(p64/pwm1o) as shown in figure 13-2 and figure 13- 7. thus, pulse out is generated by the timer match. these operation is implemented to pin, p64/pwm1o. in this mode, the bit p64/pwm1o of port selection regis- ter (psr.4) should be set to "1", and the bit pwm1e of timer1 mode register (t1cr) should be set to "0". in addi- tion, 16-bit compare output mode is available, also. this pin output the signal having a 50 : 50 duty square wave, and output frequency is same as below equation. . figure 13-12 pwm mode f comp oscillation frequency 2 prescaler value tdr 1 ) + ( --------------------------------------------------------------------------------- = 1 2 8 pwm1hr address : d5h reset value : ----0000 - - - - pwm1hr3 pwm1hr2 pwm1hr1 pwm1hr0 ---- xxxx mux 1 t1cn t1ck[1:0] t1 ( 8-bit ) t1st 0 : stop 1 : clear and start clear comparator comparator t1pdr(8-bit) pwm1hr[1:0] t1ppr(8-bit) pwm1hr[3:2] t1pdr(8-bit) sq r pol pwm1o p64/pwm1o t0 clock source f xi tm1 address : d2h reset value : 00000000 pol 16bit pwm1e cap1 t1ck1 t1ck0 t1cn t1st x010 xxxx [psr.4] period high duty high slave master bit manipulation not available x : the value "0" or "1" corresponding your operation. [t0ck] (2-bit)
hms81c2232/48 hms81c2332/48 64 feb. 2003 ver 1.00 preliminary figure 13-13 example of pwm at 4mhz figure 13-14 example of changing the period in absolute duty cycle (@4mhz) source t1 pwm1o ~ ~ ~ ~ ~ ~ 01 02 03 04 7e 7f 80 01 02 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ [pol=1] pwm1o [pol=0] duty cycle [ (1+7fh) x 250ns = 32us ] period cycle [ (3ffh+1) x 250ns = 256us, 3.9khz ] pwm1hr = 0ch t1ppr = ffh t1pdr = 80h t1ck[1:0] = 00 ( f xi ) pwm1hr3 pwm1hr2 pwm1hr1 pwm1hr0 t1ppr (8-bit) t1pdr (8-bit) period duty 1 1 ffh 00 7fh 00 clock pwm1e ~ ~ t1st ~ ~ t1cn ~ ~ 00 3ff source t1 pwm1o pol=1 duty cycle period cycle [ (1+0dh) x 2us = 28us, 35.5khz ] pwm1hr = 00h t1ppr = 0eh t1pdr = 05h t1ck[1:0] = 10 ( 1us ) 01 02 03 04 05 07 08 0a 0b 0c 0d 00 01 02 03 04 05 06 07 08 09 00 01 02 03 06 09 04 [ (04h+1) x 2us = 10us ] duty cycle [ (04h+1) x 2us = 10us ] period cycle [ (1+09h) x 2us = 20us, 50khz ] duty cycle [ (04h+1) x 2us = 10us ] write t1ppr to 09h clock 00
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 65 14. remote control timer the 8-bit remote control timer has a pulse width measurement function with a resolution of 8 bi ts. pulse width is measured from a difference in count value when the valid edge ha s been detected while the timer operates in the free-running mode. 6.3 registers controlling 8-bit remote control timer the following three types of re gisters control the 8-bit remote control timer. ? remote control timer control register (rtcr) ? remote control timer capture registers (rtcp0 and rtcp1) ? 8-bit timer register (rt) (1) remote control time r control register(rtcr) this register enables or disables the operation of the 8-bit timer (rt), and sets the count clock. tm c9 is set by using a 1-bit or 8- bit memory manipulation instruction. this register is initialized to 00 h by reset input. (2) remote control timer cap ture registers (rtcp0 and rtcp1) these 8-bit registers capture the c ontents of the 8-bit timer (rt). the capture operation is performed in synchronization with the valid edge input to the ti pin (c apture trigger). the contents of rtcp0 are retained until the next rising edge of the ti pin is de- tected. the contents of rtcp1 are retained until the next falling edge of the ti pin is detected. rtcp0 and rtcp1 can be read by using an 8-bit memory manip- ulation instruction. the values of these registers are initialized to 00 h by reset input. (3) 8-bit timer register (tm9) this 8-bit register counts the count pulse. it can be read by using an 8-bit memory manipulation inst ruction. the value of this reg- ister is initialized to 00h by reset input or by clearing the rtst bit. 6.4 operation of 8-bit remote control timer the 8-bit remote control timer ope rates as a pulse width measur- ing circuit. the width of a high-l evel or low-level external pulse input to the ti pin is measured by operating the 8-bit timer (tm9) in the free-running mode. detecti on of the valid edge is sampled every 2 cycles of the count clock selected by tcl0, tcl1 and tcl2, and the capture operation is not performed until the valid level has been detected two times. therefore, the pulse width in- put to the ti pin must be 5 or more of the count clock set by tcl0, tcl1 and tcl2, regardless of whether the level is high or low. if the pulse width is less th an 5 clocks, it cannot be detect- ed, and the capture operation is not performed. the value of timer register 9 (tm9) is loaded to and retained in the capture registers (cp90 and cp91) in synchronization with the valid edge of the pulse input to the ti pin, as shown in figure 6-3. figure 6-3 shows the timing of pulse width measurement.
hms81c2232/48 hms81c2332/48 66 feb. 2003 ver 1.00 preliminary s shown in figure 13-1 and table 13-1. figure 14-1 tm0, tm1 registers note: the rtcp0, rtdr and rt are in same address. in the capture mode, reading operation is read the rtcp0, not rt because path is opened to the rtcp0, and rtdr is only for writing operation. btcl 543210 - - rtcn initial value: --00 0000 b address: 0e7 h rtcr rtst rtck0 rtck1 rcap rtck2 bit name bit position description rcap rtcr.5 0: timer/counter mode 1: capture mode selection flag rtck2 rtck1 rtck0 rtcr.4 rtcr.3 rtcr.2 000: 8-bit timer, clock source is f xin 2 001: 8-bit timer, clock source is f xin 4 010: 8-bit timer, clock source is f xin 8 011: 8-bit timer, clock source is f xin 32 100: 8-bit timer, clock source is f xin 128 101: 8-bit timer, clock source is f xin 512 110: 8-bit timer, clock source is f xin 2048 111: ec0 (external clock) rtcn rtcr.1 0: stop the timer 1: a logic 1 starts the timer. rtst rtcr.0 0: when cleared, stop the counting. 1: when set, timer 0 count register is cleared and start again. 76543210 initial value: undefined address: 0d1 h rtdr read: count value read write: compare data write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 76543210 initial value: undefined address: 0d3 h tdr1 r/w r/w r/w r/w r/w r/w r/w r/w
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 67 . figure 14-2 block diagram of remote control timer rtfif remote falling rtcn rtcp0 (8-bit) ti pin 8 32 128 xin pin prescaler rtck[2:0] 256 512 1024 2048 rtcp1 (8-bit) rt (8-bit) capture rising edge detector falling edge detector mux 000 001 010 011 100 101 110 4096 111 noise filter clear rtdr (8-bit) comparator rtoif capture rtrif interrupt remote rising interrupt remote timer overflow interrupt btcl 543210 - - rtcn initial value: --00 0000 b address: 0e7 h rtcr rtst rtck0 rtck1 rcap rtck2 r/w r/w r/w r/w r/w r/w -- 11 x x x means don?t care 1x rcap rcap
hms81c2232/48 hms81c2332/48 68 feb. 2003 ver 1.00 preliminary figure 14-3 to measure pulse widt h in synchronization with rising edge capture capture capture capture c3 c2 c1 c0 ff h ff h c0 c1 c2 c3 00 h rtcp0 rtri ti count value rtoi t0 t1 2. t1 = (100h - c1 + c2) x 1/f count remarks : 1. t0 = (c1-c0) x 1/f count 3. f count : count clock frequency set by tcl0~ tcl2 00 h of rto
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 69 figure 14-4 to measure pulse width in synchronization with both rising and falling edge capture capture capture capture c3 c2 c1 c0 ff h ff h c1 c3 00 h rtcp1 rtri ti count value rtoi t0 t1 2. t1 = (100h - c2 + c3) x 1/f count remarks : 1. t0 = (c2-c1) x 1/f count 3. f count : count clock frequency set by tcl0~ tcl2 00 h of rto rtfi c0 c2 00 h rtcp0
hms81c2232/48 hms81c2332/48 70 feb. 2003 ver 1.00 preliminary 15. analog digital converter the analog-to-digital converter (a/d) allows conversion of an analog input signal to a correspo nding 8-bit digital value. the a/ d module has eight analog inputs, which are multiplexed into one sample and hold. the output of the sample and hold is the input into the converter, which generate s the result via successive ap- proximation. the analog supply voltage is connected to av dd of ladder resistance of a/d module. the a/d module has two registers which are the control register adcm and a/d result register ad r. the register adcm, shown in figure 15-1, controls the ope ration of the a/d converter mod- ule. the port pins can be configur ed as analog inputs or digital i/ o. to use analog inputs, each port is assigned analog input port by setting the bit ansel[7:0] in r6 func register. also it is as- signed analog input port by setting the bit ansel[11:8] in r7func register. and selected the corresponding channel to be converted by setting ads[3:0]. how to use a/d converter the processing of conversion is st art when the start bit adst is set to "1". after one cycle, it is cleared by hardware. the register adcr contains the results of th e a/d conversion. when the con- version is completed, the result is loaded into the adcr, the a/ d conversion status bit adsf is se t to "1", and the a/d interrupt flag adif is set. the block diag ram of the a/d module is shown in figure 15-2. the a/d status bit adsf is set automatically when a/d conversion is comple ted, cleared when a/d conver- sion is in process. the conversi on time takes maximum 20 us (at fxi=4 mhz) figure 15-1 a/d converter control register btcl 76543210 - adst a/d status bit analog input channel select initial value: -000 0001 b address: 0ea h adcm adsf a/d converter enable bit 0: a/d converter module turn off and current is not flow. 1: enable a/d converter r/w r/w r/w r/w r/w r 0000: channel 0 (an0) 0001: channel 1 (an1) 0010: channel 2 (an2) 0011: channel 3 (an3) 0100: channel 4 (an4) 0101: channel 5 (an5) 0110: channel 6 (an6) 0: a/d conversion is in progress 1: a/d conversion is completed a/d start bit setting this bit starts an a/d conversion. after one cycle, bit is cleared to ?0? by hardware. ads1 ads0 ads3 ads2 initial value: undefined address: 0eb h adcr a/d conversion data btcl 76543210 r r rr rr r r aden
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 71 . figure 15-2 a/d block diagram p03/an0 s/h sample & hold ?0? ?1? aden av dd adif a/d interrupt successive approximation circuit adr (8-bit) a/d result register address: eb h reset value: undefined 0000 ads[3:0] ladder resistor 8-bit dac p04/an1 0001 p05/an2 0010 p06/an3 0011 aden adcm.6 aden aden aden p22/an4 0100 p23/an5 0101 p24/an6 0110 aden aden aden
hms81c2232/48 hms81c2332/48 72 feb. 2003 ver 1.00 preliminary figure 15-3 a/d converter operation flow a/d converter cautions (1) input range of an0 to an6 the input voltage of an6 to an0 should be within the specifica- tion range. in particular, if a voltage above avdd or below avss is input (even if within the absolute maximum rating range), the conversion value for th at channel can not be indeter- minate. the conversion values of the other channels may also be affected. (2) noise countermeasures in order to maintain 8-bit resolution, attention must be paid to noise on pins av dd and an11 to an0. sinc e the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in figure 15-4 in order to reduce noise. figure 15-4 analog input pin connecting capacitor (3) pins an0/p00 to an3/p03 and an4/p22 to an6/p24 the analog input pins an6 to an0 also function as input/output port (port p7 and p2) pins. when a/d conversion is performed with any of pins an6 to an0 sele cted, be sure not to execute a port input instruction while conv ersion is in pr ogress, as this may reduce the conversion resolution. also, if digital pulses ar e applied to a pin adjace nt to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to c oupling noise. therefore, avoid ap- plying pulses to pins adjacent to the pin undergoing a/d conver- sion. (4) av dd pin input impedance a series resistor string of approximately 10k ? is connected be- tween the av dd pin and the av ss pin. therefore, if the output imp edance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the av dd pin and the av ss pin, and there will be a large reference voltage error. enable a/d converter a/d start ( adst = 1 ) nop adsf = 1 a/d input channel select analog reference select read adcr yes no an0~an6 analog input 100~1000pf
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 73 16. serial peripheral interface (spi1) the serial peripheral interface (spi) module is a serial interface useful for communicating with ot her peripheral of microcontrol- ler devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/ d converters, etc. the serial pe- ripheral interface(spi) is 8-bi t clock synchronous type and con- sists of serial i/o register, se rial i/o mode register, clock selection circuit octal counter a nd control circuit. the sout pin is designed to input and output . so serial peripheral inter- face(spi) can be operate d with minimum two pin figure 16-1 spi1 block diagram 4 16 xin pin prescaler mux sck[1:0] 00 01 10 11 sck1 pin spi1 shift input shift register sio1r clock clock octal serial communication interrupt sio1if internal bus siosf counter sck[1:0] ?11? overflow not ?11? complete timer0 overflow si1 pin iosw so1 pin sout ioswin control circuit ?0? ?1? pol 1 0 start siost clear
hms81c2232/48 hms81c2332/48 74 feb. 2003 ver 1.00 preliminary serial i/o 1 mode register(sio1m ) controls serial i/o function. according to sck1 and sck0, th e internal clock or external clock can be selected. the serial transmission operation mode is decided by setting the sm1 and sm 0, and the polarity of transfer clock is selected by setting the pol. serial i/o data register(sio1r) is a 8-bi t shift register. first lsb is send or is received. when receiving mode, serial input pin is selected by iosw. the spi allows 8-bits of data to be synchro- nously transmitted and received. to accomplish communication, typically three pins are used: - serial data in p26/si1 - serial data out p25/so1 - serial clock p27/sck1 . figure 16-2 spi1 control register btcl 76543210 iosw pol1 sio1st serial1 transmission status bit serial1 transmission clock selection initial value: 0000 0001 b address: 0e0 h sio1m sio1sf serial1 input pin selection bit 0: sin pin selection 1: ioswin pin selection r/w r/w r/w r/w r/w r 00: f xin 4 01: f xin 16 10: tmr0ov(timer0 overflow) 11: external clock 0: serial transmission is in progress 1: serial transmis sion is completed serial1 transmission start bit setting this bit starts an serial transmission. after one cycle, bit is cleared to ?0? by hardware. sck11 sck10 sm11 sm10 r/w serial1 transmission operation mode 00: normal port(p25,p26,p27) 01: sending mode(so1,p26,sck1) 10: receiving mode(p25,si1,sck1) 11: sending & receiving mode(sout,sin,sclk) initial value: undefined address: 0e1 h sio1r btcl 76543210 r/w r/w r/w r/w r/w r/w r/w r/w sending data at sending mode receiving data at receiving mode serial1 clock polarity selection bit 0: data transmission at falling edge received data latch at rising edge 1: data transmission at rising edge received data latch at falling edge r/w
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 75 16.1 transmission/receiving timing the serial transmission is started by setting sio1st(bit1 of sio1m) to ?1?. after one cycle of sck1, sio1st is cleared au- tomatically to ?0?. the serial out put data from 8-bit shift register is output at falling edge of sck1. and input data is latched at ris- ing edge of sck1 pin. when transmission clock is counted 8 times, serial i/o count er is cleared as ?0?. transmission clock is halted in ?h? state and serial i/o interrupt(ifsio1) occurred. figure 16-3 spi1 timing diagram at pol=0 figure 16-4 spi timing diagram at pol=1 d1 d2 d3 d4 d6 d7 d0 d5 d1 d2 d3 d4 d6 d7 d0 d5 sio1st sck [p27] (pol=0) so1 [p25] si1 [p26] spi1if (spi int. req) (iosw=0) d1 d2 d3 d4 d6 d7 d0 d5 ioswin [p25] (iosw=1) sio1sf (spi status) d1 d2 d3 d4 d6 d7 d0 d5 d1 d2 d3 d4 d6 d7 d0 d5 sio1st sck1 [p27] (pol=1) so1 [p25] si1 [p26] spi1if (spi int. req) (iosw=0) d1 d2 d3 d4 d6 d7 d0 d5 ioswin [p25] (iosw=1) sio1sf (spi status)
hms81c2232/48 hms81c2332/48 76 feb. 2003 ver 1.00 preliminary 16.2 the method of serial i/o y select transmission/receiving mode note: when external clock is used, the frequency should be less than 1mhz and recommended duty is 50%. t in case of sending mode, write data to be send to sio1r. ? set sio1st to ?1? to start serial transmission. note: if both transmission mode is selected and transmis- sion is performed simultaneously it would be made error. the sio1 interrupt is generated at the completion of sio1 and sio1sf is set to ?1?. in sio1 interrupt service routine, correct transmission should be tested. in case of receiving mode, the received data is acquired by reading the sio1r. 16.3 the method to test correct transmission figure 16-5 serial1 method to test transmission ldm sio1r,#0aah ;sio1r initial ;value ldm sio1m,#0011_1100b;sio1m select nop nop sio1m,#0011_1110b;sio1 start serial i/o interrupt service routine se = 0 write sio1m normal operation overrun error abnormal sio1sf 0 1 - se : interrupt enable register low ienl(bit3) - sr : interrupt request flag register low irql(bit3) sr 0 1
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 77 17. serial peripheral interface (spi3) the serial peripheral interface ( spi3) module is a serial interface useful for communicating with ot her peripheral of microcontrol- ler devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/ d converters, etc. the serial pe- ripheral interface(spi3) is 8-bi t clock synchronous type and con- sists of serial i/o register, se rial i/o mode register, clock selection circuit octal counter a nd control circuit. the sout pin is designed to input and output . so serial peripheral inter- face(spi) can be operate d with minimum two pin figure 17-1 spi3 block diagram 4 16 xin pin prescaler mux sck3[1:0] 00 01 10 11 sck3 pin spi3 shift input shift register sio3d clock clock octal serial communication interrupt sio3if internal bus sio3sf counter sck3[1:0] ?11? overflow not ?11? complete timer0 overflow sm0 so3 pin sout control circuit ?0? ?1? pol start sio3st clear
hms81c2232/48 hms81c2332/48 78 feb. 2003 ver 1.00 preliminary serial i/o mode regi ster(sio3m) controls serial i/o function. according to sck31 and sck30, the internal clock or external clock can be selected. the serial transmission operation mode is decided by setting the sm30, and th e polarity of transfer clock is selected by setting the pol3. serial i/o data register(sio3r) is a 8-bi t shift register. first lsb is send or is received. the spi 3 allows 8-bits of data to be synchronously transm itted and received. to accomplish communication, typically two pins are used: - serial3 data out p21/so3 - serial3 clock p20/sck3 . figure 17-2 spi3 control register btcl 76543210 - pol3 sio3st serial3 transmission status bit serial3 transmission clock selection initial value: 0000 0001 b address: 0dc h sio3m sio3sf r/w r/w r/w r/w r/w r 00: f xin 4 01: f xin 16 10: tmr0ov(timer0 overflow) 11: external clock 0: serial transmission is in progress 1: serial transmis sion is completed serial3 transmission start bit setting this bit starts an serial transmission. after one cycle, bit is cleared to ?0? by hardware. sck31 sck30 - sm30 r/w serial3 transmission operation mode 0: normal port(p20,p21) 1: sending mode(so3,sck3) initial value: undefined address: 0dd h sio3r btcl 76543210 r/w r/w r/w r/w r/w r/w r/w r/w sending data at sending mode serial3 clock polarity selection bit 0: data transmission at falling edge received data latch at rising edge 1: data transmission at rising edge received data latch at falling edge r/w
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 79 17.1 transmission/receiving timing the serial transmission is starte d by setting siost(bit1 of siom) to ?1?. after one cycle of sck, siost is cleared automatically to ?0?. the serial output data from 8-bit shift register is output at falling edge of sclk. and input da ta is latched at rising edge of sclk pin. when transmission cloc k is counted 8 times, serial i/ o counter is cleared as ?0?. tran smission clock is halted in ?h? state and serial i/o in terrupt(ifsio) occurred. figure 17-3 spi3 timing diagram at pol=0 figure 17-4 spi3 timing diagram at pol=1 d1 d2 d3 d4 d6 d7 d0 d5 sio3st sck3 [p20] (pol=0) so3 [p21] spi3if (spi int. req) sio3sf (spi status) d1 d2 d3 d4 d6 d7 d0 d5 sio3st sck3 [p20] (pol=1) so3 [p21] spi3if (spi int. req) sio3sf (spi status)
hms81c2232/48 hms81c2332/48 80 feb. 2003 ver 1.00 preliminary 17.2 the method of serial i/o y select transmission/receiving mode note: when external clock is used, the frequency should be less than 1mhz and recommended duty is 50%. t in case of sending mode, write data to be send to sio3r. ? set sio3st to ?1? to start serial transmission. note: if both transmission mode is selected and transmis- sion is performed simultaneously it would be made error. the sio3 interrupt is generated at the completion of sio3 and sio3sf is set to ?1?. in sio3 interrupt service routine, correct transmission should be tested. in case of receiving mode, the received data is acquired by reading the sio3r. 17.3 the method to test correct transmission figure 17-5 serial3 method to test transmission ldm sio3r,#0aah ;sio1r initial ;value ldm sio3m,#0001_1100b;sio3m select nop nop sio3m,#0001_1110b;sio3 start serial i/o interrupt service routine se = 0 write sio3m normal operation overrun error abnormal sio3sf 0 1 - se : interrupt enable register low ienl(bit3) - sr : interrupt request flag register low irql(bit3) sr 0 1
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 81 18. buzzer function the buzzer driver block consists of 6-bit binary counter, buzzer register bur, and clock source se lector. it genera tes square-wave which has very wide range frequency (480hz ~ 250khz at f xin = 4mhz) by user software. a 50% duty pulse can be output to r03/buzo pin to use for pi- ezo-electric buzzer drive. pin r 03 is assigned for output port of buzzer driver by setting the bit 3 of r0func(address 0f4 h ) to ?1?. at this time, the pin r03 mu st be defined as output mode (the bit 3 of r0io=1). example: 5khz out put at 4mhz. ldm p0io,#xxxx_x1xxb ldm bur,#0011_0010b ldm psr,#xxxx_x1xxb x means don?t care the bit 0 to 5 of bur determin es output frequency for buzzer driving. equation of frequency calc ulation is shown below. f buz : buzzer frequency f xin : oscillator frequency divide ratio: prescaler divide ratio by buck[1:0] bur: lower 6-bit value of bur. buzzer period value. the frequency of output signal is c ontrolled by the buzzer control register bur.the bit 0 to bit 5 of bur determine output frequen- cy for buzzer driving. figure 18-1 block diagram of buzzer driver figure 18-2 psr and buzzer register f buz f xin 2 divideratio bur 1 + () --------------------------------------------------------------------------- - = prescaler 8 32 16 64 bur p07/buzo pin psr internal bus line r03 port data xin pin 6-bit binary 2 6 [0de h ] [0f4 h ] 0 1 f/f 2 comparator compare data 6-bit counter mux 00 01 10 11 port selection 3 bur[5:0] bur address: 0de h reset value: undefined wwwwww source clock select 00: 8 01: 16 10: 32 11: 64 buzzer period data p07/buzo selection psr address : 0f4 h reset value : ---- 0000 b w - - 0: p07 port (turn off buzzer) 1: buzo port (turn on buzzer) ww w buck1 buck0 ww - ec0 bozo int1 int0 pwm1
hms81c2232/48 hms81c2332/48 82 feb. 2003 ver 1.00 preliminary note: bur is undefined after reset, so it must be initialized to between 1 h and 3f h by software. note that bur is a write-only register. the 6-bit counter is cleared and starts the counti ng by writing sig- nal at bur register. it is incremental from 00 h until it matches 6- bit bur value. when main-frequency is 4mhz, buzzer frequency is shown as below table. bur [5:0] bur[7:6] bur [5:0] bur[7:6] 00 01 10 11 00 01 10 11 00 01 02 03 04 05 06 07 250.000 125.000 83.333 62.500 50.000 41.667 35.714 31.250 125.000 62.500 41.667 31.250 25.000 20.833 17.857 15.625 62.500 31.250 20.833 15.625 12.500 10.417 8.929 7.813 31.250 15.625 10.417 7.813 6.250 5.208 4.464 3.906 20 21 22 23 24 25 26 27 7.576 7.353 7.143 6.944 6.757 6.579 6.410 6.250 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 1.894 1.838 1.786 1.736 1.689 1.645 1.603 1.563 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 08 09 0a 0b 0c 0d 0e 0f 27.778 25.000 22.727 20.833 19.231 17.857 16.667 15.625 13.889 12.500 11.364 10.417 9.615 8.929 8.333 7.813 6.944 6.250 5.682 5.208 4.808 4.464 4.167 3.906 3.472 3.125 2.841 2.604 2.404 2.232 2.083 1.953 28 29 2a 2b 2c 2d 2e 2f 6.098 5.952 5.814 5.682 5.556 5.435 5.319 5.208 3.049 2.976 2.907 2.841 2.778 2.717 2.660 2.604 1.524 1.488 1.453 1.420 1.389 1.359 1.330 1.302 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 10 11 12 13 14 15 16 17 14.706 13.889 13.158 12.500 11.905 11.364 10.870 10.417 7.353 6.944 6.579 6.250 5.952 5.682 5.435 5.208 3.676 3.472 3.289 3.125 2.976 2.841 2.717 2.604 1.838 1.736 1.645 1.563 1.488 1.420 1.359 1.302 30 31 32 33 34 35 36 37 5.102 5.000 4.902 4.808 4.717 4.630 4.545 4.464 2.551 2.500 2.451 2.404 2.358 2.315 2.273 2.232 1.276 1.250 1.225 1.202 1.179 1.157 1.136 1.116 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 18 19 1a 1b 1c 1d 1e 1f 10.000 9.615 9.259 8.929 8.621 8.333 8.065 7.813 5.000 4.808 4.630 4.464 4.310 4.167 4.032 3.906 2.500 2.404 2.315 2.232 2.155 2.083 2.016 1.953 1.250 1.202 1.157 1.116 1.078 1.042 1.008 0.977 38 39 3a 3b 3c 3d 3e 3f 4.386 4.310 4.237 4.167 4.098 4.032 3.968 3.907 2.193 2.155 2.119 2.083 2.049 2.016 1.984 1.953 1.096 1.078 1.059 1.042 1.025 1.008 0.992 0.977 0.548 0.539 0.530 0.521 0.512 0.504 0.496 0.488
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 83 19. fip controller/driver 19.1 function of fip controller/driver the fip controller/driver of the hms81c2232/48 has the follow- ing functions. (1) can output display signals (dma operation) by automatically reading display data. (2) the pins not used for fip di splay can be used as i/o port or output port pins (fip24 through fip52 pins only). (3) luminance can be adjusted in 8 steps by display mode register 1 (dspm1). (4) hardware for key scan application ? generates an interrupt signal (intks) indicating key scan tim- ing ? timing in which key scan data is output can be detected by key scan flag (ksf). ? whether key scan timing is inse rted or not can be selected. (5) high-voltage output buffer that can directly drive fip. (6) fip0 through fip52 pins can be connected to pull-down resis- tors by mask option (mask rom model only). the hms87c2232/48 does not have pull-down resistors) of the 53 fip output pins of the hms81c2232/48, fip24 through fip52 are multiplexed with port pins. fip0 through fip23 are dedicated output pins. fip24 through fip52 can be used as port pins when fip display is disabled by bit 7 (dsp en) of the display mode register 0 (dspm0). even when fip display is enabled, the fip output pins not used for display signal output can e used as port pins. 19.2 configuration of fip controller/driver the fip controller/driver consists of the following hardware. figure 19-1 . block diagram of fip controller/driver fip pin name multiplexed port name i/o fip24-fip31 p30-p37 output only port fip32-fip39 p40-p47 output only port fip40-fip47 p50-p57 i/o port fip48-fip52 p60-p64 i/o port table 19-1 fip output pins and multiplexed port pins internal bus line display data selector display data memory display data latch port output latch high voltage buffer fip0 fip24 fip52
hms81c2232/48 hms81c2332/48 84 feb. 2003 ver 1.00 preliminary 19.3 registers controlling fip controller/ driver the following three types of regi sters control the fip controller/ driver. ? display mode register 0 (dspm0) ? display mode register 1 (dspm1) ? display mode register 2 (dspm2) (1) display mode register 0 (dspm0) dspm0 performs the following setting. ? enables or disables display ? number of fip output pins dspm0 is set by using a 1-bit or 8-bit memory manipulation in- struction. the value of this register is set to 10 h by reset input. (2) display mode register 1 (dspm1) dspm1 performs the following setting: ? blanking width of fip output signal ? number of display patterns dspm1 is set by using a 1-bit or 8-bit memory manipulation in- struction. the value of this register is set to 01 h by reset input. (3) display mode register 2 (dspm2) dspm2 performs the following settin g. it also indi cates the status of the display timing/key scan. ? insertion of key scan timing ? display cycle (tdsp) dspm2 is set by using a 1-bit or 8-bit memory manipulation in- struction. however, only bit 7 (k sf) can be read by a 1-bit mem- ory manipulation instruction. the value of this register is initialized to 00h by reset input. figure 19-2 format of display mode register 0 item configuration display 53 control register display mode register 0 (dspm0) display mode register 1 (dspm1) display mode register 2 (dspm2) table 19-2 configuration of fip controller/driver btcl 76543210 - dspen fout1 initial value: 0-01 0000 b address: 0f0 h dspm0 fout0 r/w r/w r/w r/w r/w r fout3fout2 fout5 fout4 r/w number of fip output pins 010111 : 17~24 011111 : 25~32 100111 : 33~40 101111 : 41~48 1. be sure to set bit 6 to ?0?. enables or disables fip 0 : disables r/w 110111 : 49~53 others : setting prohibited 1 : enables 2. do not write data to the bits other than d spen when bit 7 (dspen) = 1. 3. be sure to set the output latch of the multiplexed port of a pin used for fip output to ?0?. cautions :
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 85 figure 19-3 format of display mode register 1 figure 19-4 format of display mode register 2 btcl 76543210 fblk1 fblk2 fpat1 initial value: 0000 0001 b address: 0f1 h dspm1 fpat0 r/w r/w r/w r/w r/w r fpat3 fpat2 fblk0 fpat4 r/w number of display patterns 00001 : 2 00010 : 3 00011 : 4 00100 : 5 blanking width of fip output signal r/w cautions : others : setting prohibited 00101 : 6 00110 : 7 00111 : 8 01000 : 9 01001 : 10 01010 : 11 01011 : 12 01100 : 13 01101 : 14 01110 : 15 01111 : 16 do not write data to the disp lay mode register 1 (dspm1) wh en bit 7 (dspen) of the display mode register 0 (dspm0) is 1. 001 : 02/16 010 : 04/16 011 : 06/16 100 : 08/16 101 : 10/16 110 : 12/16 111 : 14/16 000 : 01/16 btcl 76543210 ksm ksf fcyc1 initial value: 00-- --00 b address: 0f2 h dspm2 fcyc0 r/w r/w r/w r/w r/w r/w - - - r/w display cycle status of key scan cycle r 1 : key scan cycle 0 : other than key scan cycle - cautions : 1. be sure to set bits 2 through 5 to ?0?. 2. do not write data to the display mode re gister 2 (dspm2) when bit 7 (dspen) of the display mode register 0 (dspm0) is 1. 2. ( ): f x = 5.0 mhz remarks : 1. f x : main system clock oscillation frequency 00: 2 13 /f xin ( 1638us) 01: 2 12 /f xin ( 819us) 10: 2 11 /f xin ( 410us) 11: 2 10 /f xin ( 205us) selects insertion of key scan cycle 1 : inserted 0 : not inserted
hms81c2232/48 hms81c2332/48 86 feb. 2003 ver 1.00 preliminary 19.4 one display period and blanking width the fip output signals are blanke d equally at the beginning and end of the display period by the blanking width set by bits 0 through 2 (fblk0 through fblk2) of the display mode register 1 (dspm1). figure 19-5 blanking width of fip output signal fip output signal (blanking width: 1/16) fip output signal (blanking width: 2/16) fip output signal (blanking width: 4/16) 1 display period = t dsp 1/16 1/16 4/16 2/16 4/16 2/16
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 87 figure 19-6 vfd output operation timings in display mode 19.5 display data memory the display data memory is a 112- byte ram area that stores data to be displayed, and is mapped to addresses 0400 h through 046f h . the fip controller reads the data stored in the display data memory independently of the cpu operation for fip display (dma operation). the area of the display data me mory not used for display can be used as a normal ram area. at key scan timing (t ks ), all the fip output pins are cleared to ?0?, and the data of the output latches of ports 3 through 6 are out- put to fip24/p30 through fip52/p64. the address location of the display data memory is as follows: fip0 fip1 fip2 fipn ksf digit signal key scan flag t ks t cyt t dsp segment signal t dsp t cyt t ks t dig t dig : 1 display cycle : key scan timing (t ks = t dsp ) : display cycle ( t cyt = t dsp x displayed digit + 1) : width of digit singanl pulse n : displayed digit -1 (digits 2 to 16 can be selected using the dspm1)
hms81c2232/48 hms81c2332/48 88 feb. 2003 ver 1.00 preliminary ? with 53 fip output pins and 16 patterns the addresses of the display da ta memory corresponding to the data output at each di splay timing (t0 through t15) are as shown in figure 19-7 (for example, t0 = 0400 h through 0406 h , and t1 = 0407 h through 040d h ). when 53 fip output pins (fip0 through fip52) are used, one block of display data consists of 7 bytes. fip output pins 0 (fip0) through 52 (fip52) correspond to one block of display data se- quentially, starting from the least significant bit toward the most significant bit. figure 19-7 relation between address location of display data memory and fip output hms81c2232/48 (with 53 fip output pins and 16 patterns) 19.6 key scan flag and key scan data key scan flag the key scan flag (ksf) is set to 1 during key scan timing, and is automatically reset to 0 at display timing. ksf is mapped to bit 7 of the display mode register 2 (dspm2) and can be tested in 1-bit units. it cannot be written, however. by testing ksf, it can be determin ed whether key scan timing is in progress, and whether key input da ta is correct can be checked. whether key scan timing is inserted or not ca n be selected by us- ing the key scan timing insertion specification flag(ksm) (bit 6 of the display mode register 2 (dspm2)). key scan data data stored to ports 3 through 6 are output from the fip24 through fip52 pins during key scan timing. note: if scanning is performed in such a manner that both a segment and a digit turn on during keyscan timing, the display may flicker. 0400 h ~0406 h t00 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 54h 55h 56h 57h 58h 59h 5ah 5bh 5ch 5dh 5eh 5fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6ah 6bh 6ch 6dh 6eh 6fh 0407 h ~040d h 040e h ~0414 h 0415 h ~041b h 0454 h ~045a h 045b h ~0461 h 0462 h ~0468 h 0469 h ~046f h 7- - - - - - -0 fip output pins 52 ---48 fip output pins t01 t02 t03 t12 t13 t14 t15 t ks address display timing
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 89 figure 19-8 relation between address location of display data memory and fip output hms81c2332/48 (with 41 fip output pins and 16 patterns) 0400 h ~0406 h 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 54h 55h 56h 57h 58h 59h 5ah 5bh 5ch 5dh 5eh 5fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6ah 6bh 6ch 6dh 6eh 6fh 0407 h ~040d h 040e h ~0414 h 0415 h ~041b h 0454 h ~045a h 045b h ~0461 h 0462 h ~0468 h 0469 h ~046f h 7 ------- 0 fip output pins 52-50 fip output pins address 15 ------- 8 18-16 31 ------ 24 36--32 45----40 t00 t01 t02 t03 t12 t13 t14 t15 t ks display timing
hms81c2232/48 hms81c2332/48 90 feb. 2003 ver 1.00 preliminary figure 19-9 relationship between display data memory and fip outp ut with 8 segments-11 digits displayed 0402 h , 0401 h , 0400 h t00 t01 t02 t03 display ram address display f f ? btcl xxxx00 x0 btcl 000000 00 btcl 000001 00 btcl xxxx00 x0 btcl 000000 00 btcl 000000 01 btcl xxxx00 x0 btcl 000000 00 btcl 000010 00 btcl xxxx00 x0 btcl 000000 00 btcl 000100 00 btcl xxxx00 x0 btcl 000000 00 btcl 001000 00 btcl xxxx00 x0 btcl 000000 00 btcl 010000 00 btcl xxxx00 x0 btcl 000000 00 btcl 000000 10 btcl xxxx00 x0 btcl 000001 00 btcl 000000 00 btcl xxxx00 x0 btcl 000000 01 btcl 000000 00 btcl xxxx00 x0 btcl 000010 00 btcl 000000 00 754320 61 15 13 12 11 10 8 14 9 18 16 17 hf g ecba d btcl xxxx00 x0 btcl 000000 00 btcl 100000 00 0409 h , 0408 h , 0407 h 0410 h , 040f h , 040e h 0417 h , 0416 h , 0415 h 041e h , 041d h , 041c h 0425 h , 0424 h , 0423 h 042c h , 042b h , 042a h 0433 h , 0432 h , 0431 h 043a h , 0439 h , 0438 h 0441 h , 0440 h , 043f h 0448 h , 0447 h , 0446 h digit part segment part t04 t05 t06 t07 t08 t09 t10 timing
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 91 figure 19-10 relationship between display data memory and fip output with 13 segments-11 digits displayed 0402 h , 0401 h , 0400 h t00 t01 t02 t03 display ram address display f f ? btcl 000000 00 btcl 000000 00 btcl 000001 00 btcl 000000 00 btcl 000000 00 btcl 000000 01 btcl 000000 00 btcl 000000 00 btcl 000010 00 btcl 000000 00 btcl 000000 00 btcl 000100 00 btcl 000000 00 btcl 000000 00 btcl 001000 00 btcl 000000 00 btcl 000000 00 btcl 010000 00 btcl 000000 00 btcl 000000 00 btcl 000000 10 btcl 000000 00 btcl 000001 00 btcl 000000 00 btcl 000000 00 btcl 000000 01 btcl 000000 00 btcl 000000 00 btcl 000010 00 btcl 000000 00 754320 61 15 13 12 11 10 8 14 9 23 21 20 19 18 16 22 17 mkjih f lg ecba d btcl 000000 00 btcl 000000 00 btcl 100000 00 0409 h , 0408 h , 0407 h 0410 h , 040f h , 040e h 0417 h , 0416 h , 0415 h 041e h , 041d h , 041c h 0425 h , 0424 h , 0423 h 042c h , 042b h , 042a h 0433 h , 0432 h , 0431 h 043a h , 0439 h , 0438 h 0441 h , 0440 h , 043f h 0448 h , 0447 h , 0446 h digit part segment part t04 t05 t06 t07 t08 t09 t10 timing
hms81c2232/48 hms81c2332/48 92 feb. 2003 ver 1.00 preliminary 20. interrupts the hms81c2232/48 interrupt circ uits consist of interrupt en- able register (ienh, ienl), interrupt request flags of irqh, irql, priority circuit, and master enable flag (?i? flag of psw). nine interrupt source s are provided. the configuration of inter- rupt circuit is shown in figure 20-2. the external interrupts int0 and int1 each can be transition-ac- tivated (1-to-0 or 0-to-1 tr ansition) by selection ieds. the flags that actually generate these interrupts are bit int0f and int1f in register irqh. when an external interrupt is generated, the flag that generated it is cleared by the hardware when the ser- vice routine is vectored to only if the interrupt was transition-ac- tivated. the timer 0 ~ timer 1 interrupts are generated by txif which is set by a match in their respective timer/counter register. the ba- sic interval timer interrupt is generated by bitif which is set by an overflow in th e timer register. the ad converter interrupt is ge nerated by adif which is set by finishing the analog to digital conversion.the watchdog timer in- terrupt is generated by wdtif wh ich set by a match in watchdog timer register.the basi c interval timer inte rrupt is generated by bitif which are set by a overflow in the timer counter register. the interrupts are controlled by the interrupt master enable flag i-flag (bit 2 of psw on page 27), the interrupt enable register (ienh, ienl), and the interrupt request flags (in irqh and irql) except power-on reset and software brk interrupt. below table shows the interrupt priority. figure 20-1 interrupt request flag reset/interrupt symbol priority hardware reset external interrupt 0 external interrupt 1 remote timer rising remote timer falling remte timer overflow key scan interrupt sio1 interrupt sio3 interrupt timer/counter 0 timer/counter 1 adc interrupt watchdog timer basic interval timer reset intp0 intp1 rtr rtf rto ks sio1 sio3 timer0 timer1 adc wdt bit - 1 2 3 4 5 6 7 8 9 10 11 12 13 r/w int0if initial value: 0000 0000 b address: 0e4 h irqh int1if msb r/w remote control falling edge interrupt request flag wdtif r/w t0if initial value: 00-- 000- b address: 0e5 h irql t1if msb lsb - - adcif r/w remote control rising edge interrupt request flag - r/w r/w r/w r/w - -- basic interval imer interrupt request flag watchdog timer interrupt request flag a/d conver interrupt request flag external interrupt 1 request flag external interrupt 0 request flag lsb r/w rtoif kscif r/w r/w r/w rtrif rtfif sio1if sio3if bitif r/w timer/counter 1 interrupt request flag timer/counter 0 interrupt request flag sio3 communication interrupt request flag sio1 communication interrupt request flag key scanl interrupt request flag remote timer overflow interrupt request flag
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 93 vector addresses are shown in figure 8-6 on page 29. interrupt enable registers are shown in figure 20-3. these registers are composed of interrupt enable flags of each interrupt source and these flags determines whether an interrupt will be accepted or not. when enable flag is ?0?, a corresponding interrupt source is prohibited. note that psw contains also a master enable bit, i- flag, which disables all interrupt s at once. figure 20-2 block diagram of interrupt remote risging intp1 intp0 int0if ienh interrupt enable interrupt enable irqh irql interrupt vector address generator internal bus line register (lower byte) internal bus line register (higher byte) release stop to cpu interrupt master enable flag i-flag ienl priority control i-flag is in psw, it is cleared by "di", set by "ei" instruction. when it goes interrupt service, i-flag is cleared by hardware, thus any other interrupt are inhibited. when interrupt service is completed by "reti" instruction, i-flag is set to "1" by hardware. [0e2 h ] [0e3 h ] [0e4 h ] [0e5 h ] int1if rtrif remote falling rtfif timer1 t1if bitif wdtif adc bit watch dog timer adcif sio1 rtoif ksif sio1if sio3 sio3if remote timer key scan t0if timer0
hms81c2232/48 hms81c2332/48 94 feb. 2003 ver 1.00 preliminary figure 20-3 inte rrupt enable flag 0: disable 1: enable value r/w int0e initial value: 0000 0000 b address: 0e2 h ienh int1e msb r/w remote control falling edge interrupt enable flag wdte r/w t0e initial value: 00-- 000- b address: 0e3 h ienl t1e msb lsb - - adce r/w remote control rising edge interrupt enable flag - r/w r/w r/w r/w - -- basic interval imer interrupt enable flag watchdog timer interrupt enable flag a/d conver interrupt enable flag external interrupt 1 enable flag external interrupt 0 enable flag lsb r/w rtoe ksce r/w r/w r/w rtre rtfe sio1e sio3e bite r/w timer/counter 1 interrupt enable flag timer/counter 0 interrupt enable flag sio3 communication interrupt enable flag sio1 communication interrupt enable flag key scanl interrupt enable flag remote timer overflow interrupt enable flag 0: disable 1: enable value
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 95 20.1 interrupt sequence an interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ?0? by a reset or an instruction. inter- rupt acceptance sequence requires 8 f xin (2 s at f main =4.19mhz) after the completion of the current instruction execution. the interrupt service task is terminated upon execu- tion of an interrupt return instruction [reti]. interrupt acceptance 1. the interrupt master enable flag (i-flag) is cleared to ?0? to temporarily disable the acceptance of any follow- ing maskable interrupts. when a non-maskable inter- rupt is accepted, the ac ceptance of any following interrupts is temporarily disabled. 2. interrupt request flag for the interrupt source accepted is cleared to ?0?. 3. the contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. the stack po inter decreases 3 times. 4. the entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. the instruction stored at th e entry address of the inter- rupt service program is executed. figure 20-4 timing chart of interrupt acceptance and interrupt return instruction a interrupt request is not accepted until the i-flag is set to ?1? even if a requested interrupt has higher priority than that of the current interrupt being serviced. when nested interrupt service is required, th e i-flag should be set to ?1? by ?ei? instruction in the interrupt service program. in this case, acceptable interrupt source s are selectively enabled by the individual interrupt enable flags. saving/restoring general-purpose register during interrupt acceptance proc essing, the program counter and the program status word are auto matically saved on the stack, but accumulator and other registers ar e not saved itself. these regis- ters are saved by the software if necessary. also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. the following method is used to save/restore the general-purpose v.l. system clock address bus pc sp sp-1 sp-2 v.h. new pc v.l. data bus not used pch pcl psw adl op code adh instruction fetch internal read internal write interrupt processing step interrupt service task v.l. and v.h. are vector addresses. adl and adh are start addresses of interrupt service routine as vector contents. basic interval timer 012 h 0e3 h 0ffe6 h 0ffe7 h 0e h 2e h 0e312 h 0e313 h entry address correspondence between vector table address for bit interrupt and the entry address of the interrupt service program. vector table address
hms81c2232/48 hms81c2332/48 96 feb. 2003 ver 1.00 preliminary registers. example: register save us ing push and pop instructions general-purpose register save/res tore using push and pop instruc- tions; 20.2 brk interrupt software interrupt can be invoke d by brk instruction, which has the lowest priority order. interrupt vector address of brk is shared with the vector of tcall 0 (refer to program memo ry section). when brk inter- rupt is generated, b-flag of ps w is set to distinguish brk from tcall 0. each processing step is determin ed by b-flag as shown in figure 20-5. figure 20-5 execution of brk/tcall0 intxx: push a push x push y ;save acc. ;save x reg. ;save y reg. interrupt processing pop y pop x pop a reti ;restore y reg. ;restore x reg. ;restore acc. ;return main task interrupt service task saving registers restoring registers acceptance of interrupt interrupt return b-flag brk interrupt routine reti tcall0 routine ret brk or tcall0 =0 =1
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 97 20.3 multi interrupt if two requests of different priority levels are received simulta- neously, the request of higher prio rity level is serviced. if re- quests of the interrupt are received at the same time simultaneously, an internal pol ling sequence determines by hard- ware which request is serviced. figure 20-6 execution of multi interrupt however, multiple processing through software for special fea- tures is possible. generally when an interrupt is accepted, the i- flag is cleared to disable any furt her interrupt. but as user sets i- flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. example: during timer1 interrupt is in progress, int0 interrupt serviced without any suspend. timer1: push a push x push y ldm ienh,#80h ; enable int0 only ldm ienl,#0 ; disable other ei ; enable interrupt : : : : : : ldm ienh,#0f0h ; enable all interrupts ldm ienl,#0f0h pop y pop x pop a reti enable int0 timer 1 service int0 service main program service occur timer1 interrupt occur int0 ei disable other enable int0 enable other in this example, the int0 interrupt can be serviced without any pending, even timer1 is in progress. because of re-setting the interrupt enable registers ienh,ienl and master enable "ei" in the timer1 routine.
hms81c2232/48 hms81c2332/48 98 feb. 2003 ver 1.00 preliminary 20.4 external interrupt the external interrupt on int0 a nd int1 pins are edge triggered depending on the edge selecti on register ieds (address 0f8 h ) as shown in figure 20-7. the edge detection of external in terrupt has three transition acti- vated mode: rising edge, fa lling edge, and both edge. figure 20-7 external interrupt block diagram int0 and int1 are multiplexed with general i/o ports (p00 and p01). to use as an external inte rrupt pin, the bit of psr should be set to ?1? correspondingly. example: to use as an int0 and int1 : : ; **** set port as an input port r00,r01 ldm r0io,#1111_1100b ; ; **** set port as an interrupt port ldm psr,#0000_0011b ; ; **** set falling-edge detection ldm ieds,#0000_0101b : : : response time the int0 and int1 edge are latc hed into int0if and int1if at every machine cycle. the values are not actually polled by the circuitry until the next machine cy cle. if a request is active and conditions are right for it to be acknowledged, a hardware subrou- tine call to the requested service routine will be the next instruc- tion to be executed. the div itse lf takes twelve cycles. thus, a minimum of twelve complete machine cycles elapse between ac- tivation of an external interrupt request and the beginning of ex- ecution of the first instruction of the service routine. figure 20-8 shows interr upt response timings. figure 20-8 interrupt response timing diagram int1if int1 pin int1 interrupt ieds [0e6h] int0if int0 pin int0 interrupt edge selection register 2 2 interrupt goes active interrupt latched interrupt processing interrupt routine 8 f xin max. 12 f xin
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 99 figure 20-9 psr and ieds registers btcl wwwwwwww - - - intp1 0: p00 1: intp0 initial value: ---- 0000 b address: 0f4 h psr pwm1 intp0 ec0 buzo 0: p01 1: intp1 0: p07 1: buzo 0: p03 1: ec0 lsb msb btcl r/w r/w r/w r/w - - -ied0h initial value: ---- 0000 b address: 0e6 h ieds -ied0l ied1l ied1h lsb msb edge selection register 00: reserved 01: falling (1-to-0 transition) 10: rising (0-to-1 transition) 11: both (rising & falling) int0 int1 0: p64 1: pwm1
hms81c2232/48 hms81c2332/48 100 feb. 2003 ver 1.00 preliminary 21. power saving mode the gms81c2232/48 has two power-down modes. in power- down mode, power consumption is reduced considerably that in battery operation battery life ca n be extended a lot. for applica- tions where power cons umption is a critical factor, device pro- vides two kinds of power saving functions, stop mode and sleep mode. table 21-1 shows the status of each power saving mode. sleep mode is entered by setting bit 0 of smr(sleep mode register), an d stop mode is entered by stop instruction. 21.1 sleep mode in this mode, the internal osci llation circuits remain active. oscillation continues and peripherals are operate normally but cpu stops. movement of all peri pherals is shown in table 20-1. sleep mode is entered by setting the bit slp of smr to ?1?. (this register should be written by byte operation. if this register is set by bit manipulat ion instruction, for ex ample "set1" or "clr1" instruction, it may be undesired operation) . it is released by re- set or interrupt. to be releas e by interrupt, in terrupt should be enabled before sleep mode. note: after sleep instruction, at least two or more nop instruction should be written ex) ldm smr,#0000_0001b nop nop nop figure 21-1 sl eep mode register release the sleep mode the exit from sleep mode is ha rdware reset or all interrupts. reset re-defines all the control registers but does not change the on-chip ram. interrupts allow both on-chip ram and control registers to retain their values. if i-flag = 1, the normal interrupt response takes place. if i-flag = 0, the chip will resume execution starting with the instruction fol- lowing the sleep instruction. it wi ll not vector to interrupt serv- ice routine. (refer to figure 23-5) when exit from sleep mode by reset, enough oscillation stabi- lization time is requi red to normal operation. figure 21-3 shows the timing diagram. when release the sleep mode, the basic in- terval timer is activated on wake -up. it is increased from 00 h until ff h . the count overflow is set to start normal operation. there- fore, before sleep instruction, user must be set its relevant pres- caler divide ratio to have l ong enough time (more than 20msec). this guarantees that os cillator has st arted and stabilized. by inter- rupts, exit from sleep mode is shown in figure 21-2. by reset, exit from sleep mode is s hown in figure 21-3. 76543210 slp initial value: ---- ---0 b address: 0fb h smr w power fail status 0: not sleep mode 1: sleep mode this bit becomes 0 automatically after one machine cycle.
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 101 . figure 21-2 sleep mode release timing by external interrupt figure 21-3 timing of sl eep mode release by reset 21.2 stop mode in the stop mode, the on-chip oscill ator is stopped. with the clock frozen, all functions are stopped, but the on-chip ram and con- trol registers are held. the port pi ns out the values held by their respective port data register, port direction registers. oscillator stops and the systems internal operations are all held up. ? the states of the ram, registers, and latches valid immediately before the system is put in the stop state are all held. ? the program counter stop the address of the instruction to be execut ed after the instruction "stop" which starts the stop operating mode. note: the stop mode is activated by execution of stop instruction after clearing t he bit wakeup of ckctlr to ?0?. (this register should be written by byte operation. if this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation) in the stop mode of operation, v dd can be reduced to minimize power consumption. care must be taken, however, to ensure that v dd is not reduced before the stop mode is invoked, and that v dd is restored to its normal ope rating level, before the stop mode is terminated. the reset should not be activated before v dd is restored to its oscillator (x in pin) ~ ~ normal operation sleep operation ~ ~ ~ ~ ~ ~ ~ ~ external interrupt internal clock sleep instruction executed ~ ~ normal operation ~ ~ ~ ~ ~ ~ sleep instruction stabilization time t st = 65.5ms @4mhz internal ~ ~ ~ ~ ~ ~ resetb resetb oscillator (xi pin) ~ ~ cpu clock ~ ~ ~ ~ execution normal operation sleep operation normal operation
hms81c2232/48 hms81c2332/48 102 feb. 2003 ver 1.00 preliminary normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. note: after stop instruction, at least two or more nop in- struction shoul d be written ex) ldm ckctlr,#0000_1110b nop ldm stpc,#0101_1010b nop stop nop nop in the stop operation, the dissi pation of the power associated with the oscillator and the intern al hardware is lowered; however, the power dissipation associated with the pin interface (depend- ing on the external circuitry and program) is not directly deter- mined by the hardware operation of the stop feature. this point should be little current flows when the input level is stable at the power voltage level (v dd /v ss ); however, when the input level gets higher than the power voltage level (by approximately 0.3 to 0.5v), a current begins to flow. therefore, if cutting off the out- put transistor at an i/o port puts the pin signal into the high-im- pedance state, a current flow ac ross the ports input transistor, requiring to fix the level by pull-up or other means. figure 21-4 stop control register btcl 76543210 0 1 initial value: 0000 0000 b address: 0ff h stpc 0 wwwwww 1 0 0 1 1 1. to get into stop mode, stop control registor must be enabled just before stop instruction. 2. when stop mode is released, stop control registor(stpc) value is cleared automatically. 3. it is prohibited to wirte another value into stpc. cautions : ww peripheral stop mode sleep mode cpu stop stop ram retain retain basic interval timer halted operates continuously watchdog timer stop stop timer/event0,1 halted(only when the event counter mode is enable, timer operates normaly) operates continuously vfd controller stop stop sio3,buz,adc,remote timer stop stop sio1 only operate with external cloc k only operate with external clock oscillation stop(xin=l, xout=h) oscillation i/o ports retain retain control registers retain retain internal circuit stop mode sleep mode prescaler retain active address data bus retain retain release source reset, timer interrupt(ec0), sio1(exter- nal clock), external interrupt reset, all interrupts table 21-1peripheral operation during power saving mode
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 103 release the stop mode the exit from stop mode is hardwa re reset or external interrupt. reset re-defines all the control registers but does not change the on-chip ram. external interrupts allow both on-chip ram and control registers to retain their values. if i-flag = 1, the normal interrupt response takes place. if i-flag = 0, the chip will resume execution starting with the instruction fol- lowing the stop instruction. it will not vector to interrupt service routine. (refer to figure 21-5) when exit from stop mode by ex ternal interrupt , enough oscilla- tion stabilization time is require d to normal operation. figure 21- 6 shows the timing diagram. when release the stop mode, the ba- sic interval timer is activated on wake-up. it is increased from 00 h until ff h . the count overflow is set to start normal opera- tion. therefore, before stop instruction, user must be set its rel- evant prescaler divide ratio to have long enough time (more than 20msec). this guarantees that oscillator has st arted and stabi- lized. by reset, exit from stop mode is shown in figure . figure 21-5 stop releasing flow by interrupts iexx =0 =1 stop instruction stop mode interrupt request stop mode release i-flag =1 interrupt service routine next instruction =0 master interrupt enable bit psw[2] corresponding interrupt enable bit (ienh, ienl)
hms81c2232/48 hms81c2332/48 104 feb. 2003 ver 1.00 preliminary . figure 21-6 stop mode release timing by external interrupt figure 21-7 timing of stop mode release by reset 21.3 internal rc-oscillated watchdog timer mode in the internal rc-oscillated watchdog timer mode, the on-chip oscillator is stopped. but internal rc oscillation circuit is oscillated in th is mode. the on-chip ram and control registers are held. the port pins out the values held by their respective port data register, port direction regis- ters. the internal rc-oscillated watchdog timer mode is activated by execution of stop instruction after set- ting the bit wakeup and rcwdt of ckctlr to " 01 ". (this register should be written by byte operation. if this register is set by bit manipulation instruction, for example "set1" or "clr1" in struction, it may be unde- sired operation) note: caution: after stop instruction, at least two or more nop instruction should be written ex) ldm wdtr ,#1111_1111b ldm ckctlr ,#0 01 0_1110b nop ldm stpc,#0101_1010b nop stop nop nop the exit from internal rc-oscillated watchdog timer mode is hardware reset or external interrupt. reset re-de- fines all the control registers but does not change the on- chip ram. external interrupts allow both on-chip ram before executing stop instruction, basic interval timer must be set oscillator (x in pin) ~ ~ n 0 bit counter n+1 n+2 n+3 ~ ~ normal operation stop operation normal operation 1 fe ff 0 12 ~ ~ ~ ~ ~ ~ t st > 20ms ~ ~ ~ ~ external interrupt internal clock clear stop instruction executed ~ ~ ~ ~ ~ ~ properly by software to get stabilization time which is longer than 20ms. by software ~ ~ ~ ~ stop mode time can not be control by software oscillator (xi pin) ~ ~ ~ ~ ~ ~ stop instruction execution stabilization time t st = 64ms @4mhz internal clock internal ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ resetb resetb
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 105 and control registers to retain their values. if i-flag = 1, the normal inte rrupt response takes place. in this case, if the bit wdton of ckctlr is set to "0" and the bit wdte of ienh is set to "1", the device will execute the watchdog timer interrupt service routine.(figure 21-8) however, if the bit wdton of ckctlr is set to "1", the device will generate the inte rnal reset signal and exe- cute the reset processing. (fig ure 21-9) -flag = 0, the chip will resume execution starting with the instruction follow- ing the stop instruction. it will not vector to interrupt service routine.(ref er to figure 21-5) when exit from internal rc-oscillated watchdog timer mode by external interrupt, the oscillation stabilization time is required to normal operation. figure 21-8 shows the timing diagram. when release the internal rc-oscil- lated watchdog timer mode, the basic interval timer is ac- tivated on wake-up. it is increased from 00 h until ff h . the count overflow is set to star t normal operation. therefore, before stop instruction, user must be set its relevant pres- caler divide ratio to have long enough time (more than 20msec). this guarantees that oscillator has started and stabilized. by reset, exit from internal rc-oscillated watchdog timer mode is shown in figure 21-9. figure 21-8 internal rcwdt mode releas ing by external interrupt or wdt interrupt figure 21-9 internal rcwdt mode releasing by reset ~ ~ rcwdt mode normal operation oscillator (xi pin) ~ ~ ~ ~ n+1 nn+2 00 01 fe ff 00 00 n-1 n-2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ clear basic interval timer stop instruction execution normal operation stabilization time t st > 20ms internal clock external interrupt bit counter ~ ~ internal rc clock ( or wdt interrupt ) ~ ~ oscillator (xi pin) ~ ~ ~ ~ ~ ~ ~ ~ internal clock internal rc clock time can not be control by software ~ ~ stop instruction execution stabilization time t st = 64ms @4mhz internal ~ ~ ~ ~ ~ ~ reset by wdt reset reset rcwdt mode
hms81c2232/48 hms81c2332/48 106 feb. 2003 ver 1.00 preliminary 21.4 minimizing current consumption the stop mode is designed to reduce power consumption. to minimize current drawn during st op mode, the user should turn- off output drivers that are sourcing or sinking current, if it is prac- tical. . figure 21-10 application example of unused input port figure 21-11 application example of unused output port note: in the stop operation, the power dissipation asso- ciated with the oscillator and the internal hardware is low- ered; however, the power diss ipation associated with the pin interface (depending on the external circuitry and pro- gram) is not directly determined by the hardware operation of the stop feature. this point should be little current flows when the input level is stable at the power voltage level (v dd /v ss ); however, when the in put level becomes higher than the power voltage level (by approximately 0.3v), a cur- rent begins to flow. therefore, if cutting off the output tran- sistor at an i/o port puts the pin signal into the high- impedance state, a current flow across the ports input tran- sistor, requiring it to fix the level by pull-up or other means. it should be set properly in orde r that current flow through port doesn't exist. input pin v dd gnd i v dd x weak pull-up current flows v dd internal pull-up input pin i v dd x very weak current flows v dd o o open open i=0 o i=0 o gnd when port is configured as an input, input level should be closed to 0v or 5v to avoid power consumption. output pin gnd i in the left case, much current flows from port to gnd. x on off output pin gnd i in the left case, tr. base current flows from port to gnd. i=0 x off on v dd l on off open gnd v dd l on off to avoid power consumption, there should be low output on off o o v dd o to the port .
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 107 first conseider the setting to input mode. be sure that there is no current flow after considering its relationship with external cir- cuit. in input mode, the pin im pedance viewing from external mcu is very high that the current doesn?t flow. but input voltage level should be v ss or v dd . be careful that if unspecified voltage, i.e. if unfirmed voltage level (not v ss or v dd ) is applied to input pin, ther e can be little current (max. 1ma at around 2v) flow. if it is not appropriate to set as an input mode, then set to output mode considering there is no curre nt flow. setting to high or low is decided considering its relations hip with external circuit. for example, if there is external pull-up resistor then it is set to output mode, i.e. to high, and if there is external pull-down register, it is set to low.
hms81c2232/48 hms81c2332/48 108 feb. 2003 ver 1.00 preliminary 22. oscillator circuit the hms81c2232/48 has two oscilla tion circuits internally. x in and x out are input and output for main frequency. respectively, inverting amplifier whic h can be configured for being used as an on-chip oscillator, as shown in figure 22-1. figure 22-1 oscillation circuit oscillation circuit is designed to be used either with a ceramic resonator or crystal os cillator. since each cr ystal and ceramic res- onator have their own characteris tics, the user should consult the crystal manufacturer for appropri ate values of external compo- nents. oscillation circuit is designed to be used either with a ceramic resonator or crystal os cillator. since each cr ystal and ceramic res- onator have their own characteris tics, the user should consult the crystal manufacturer for appropri ate values of external compo- nents. in addition, see figure 22-2 for the layout of the crystal. note: minimize the wiring length. do not allow the wiring to intersect with other signal conductors. do not allow the wir- ing to come near changing high current. set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground it to any ground pattern where high cur- rent is present. do not fetc h signals from the oscillator. figure 22-2 layout of oscillator pcb circuit x out x in v ss recommend c1,c2 = 30pf c1 c2 x out x in external clock open external oscillator crystal or ceramic oscillator 4.19mhz crystal oscillator ceramic resonator c1,c2 = 30pf x out x in
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 109 23. reset the hms81c20xxa have two types of reset generation proce- dures; one is an external reset i nput, the other is a watch-dog tim- er reset. table 23-1 shows on -chip hardware initialization by reset action. table 23-1 initializing internal status by reset action 23.1 external reset input the reset input is the reset pin, which is the input to a schmitt trigger. a reset in accomplish ed by holding the reset pin low for at least 8 oscillat or periods, within th e operating voltage range and oscillation stable, it is applied, and the internal state is initial- ized. after reset, 64m s (at 4 mhz) add with 7 oscillator periods are required to start execution as shown in figure 23-2. internal ram is not affe cted by reset. when v dd is turned on, the ram content is indeterminat e. therefore, this ram should be initialized before read or tested it. when the reset pin input goes to high, the reset operation is re- leased and the program execution starts at the vector address stored at addresses fffe h - ffff h . a connection for simple power-on -reset is shown in figure 23-1. figure 23-1 simple power-on-reset circuit figure 23-2 timi ng diagram after reset 23.2 watchdog timer reset refer to ?12. watchdog timer? on page 48. on-chip hardware initial value on-chip hardware initial value program counter (pc) (ffff h ) - (fffe h ) peripheral clock off ram page register (rpr) 0 watchdog timer disable g-flag (g) 0 control registers refer to table 8-1 on page 28 operation mode main-frequency cl ock power fail detector disable 7036p v cc 10uf + 10k ? to the reset pin main program oscillator (x in pin) ? ? fffe ffff stabilization time t st = 62.5ms at 4.19mhz reset address data 1 2 3 4 5 6 7 ?? start ? ? ? fe ? adl adh op bus bus reset process step ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t st = x 256 f main 1024 1
hms81c2232/48 hms81c2332/48 110 feb. 2003 ver 1.00 preliminary 24. power fail processor the hms81c2232/48 has an on-chip power fail detection cir- cuitry to immunize against power noise. a configuration register, pfdr, can enable or disable th e power fail detect circuitry. whenever v dd falls close to or below power fail voltage for 100ns, the power fail situation ma y reset or freeze mcu accord- ing to pfdm bit of pfdr. refer to ?7.4 dc electrical character- istics? on page 20. in the in-circuit emulator, power fail function is not implemented and user can not experi ment with it. therefore, after final devel- opment of user program, this function may be experimented or evaluated. note: user can select power fail voltage level according to pfd0, pfd1 bit of config register(703f h ) at the otp (hms87c20xxa) but must select the power fail voltage level to define pfd option of ?mask order & verification sheet? at the mask chip(hms81c2232/48). because the power fail voltage level of mask chip (hms81c20xxa) is determined according to mask option. note: if power fail voltage is selected to 3.0v on 3v oper- ation, mcu is freezed at all the times. table 24-1 power fail processor . figure 24-1 power fail voltage detector register power failfunction otp mask enable/disable pfdis flag pfdis flag level selection pfs0 bit pfs1 bit mask option pfdm 76543210 pfs initial value: ---- -100 b address: 0ef h pfdr r/w r/w r/w pfdis operation mode 0 : normal operation regardless of power fail 1 : mcu will be reset by power fail detection disable flag 0: power fail detection enable 1: power fail detection disable power fail status 0: normal operate 1: set to ?1? if power fail is detected
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 111 figure 24-2 example s/w of reset flow by power fail figure 24-3 power fail processor situations funtion execution initialize ram data pfs =1 no reset vector initialize all ports initialize registers ram clear yes skip the initial routine pfs = 0 internal reset internal reset internal reset v dd v dd v dd v pfd max v pfd min v pfd max v pfd min v pfd max v pfd min 64ms 64ms t <64ms 64ms when pfr = 1
hms81c2232/48 hms81c2332/48 112 feb. 2003 ver 1.00 preliminary 25. otp programming 25.1 device configuration area the device configuration area can be programmed or left un- programmed to select device confi guration such as security bit. sixteen memory locations (3070 h ~ 307f h ) are designated as customer id recording locations where the user can store check- sum or other customer identification numbers. this area is not accessible dur ing normal execution but is reada- ble and writable during program / verify. figure 25-1 device configuration area device 3070 h 3070 h 307f h 307f h id config configuration area 3071 h id 3072 h id 3073 h id 3074 h id 3075 h id 3076 h id 3077 h id 3078 h id 3079 h id 307a h id 307b h id 307c h id 307d h id 307e h id 76543210 initial value: ---- -000 b address: 307f h config code protect 0 : lock disalbe 1 : lock enable pfd level selection 00: pfd = 2.7v 01: pfd = 2.7v pfs0 pfs1 10: pfd = 3.0v 11: pfd = 2.4v lock
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 113 pin no. user mode eprom mode 80mqfp 80tqfp 64sdip 64mqfp 64lqfp pin name pin name description 6 14 7 6 reset vpp programming power (0v, 11.5v) 3 11 4 3 xin pxen otp clock 7158 7p27 ctl3 program/verify/read control 8169 8p26 ctl2 917109p25 ctl1 program mode control 10 18 11 10 p24 ctl0 15 19 12 11 p00 a_d0 address input data input/output a8 a0 d0 16 20 13 12 p01 a_d1 a9 a1 d1 17 21 14 13 p02 a_d2 a10 a2 d2 19 23 16 15 p03 a_d3 a11 a3 d3 20 24 17 16 p04 a_d4 a12 a4 d4 21 25 18 17 p05 a_d5 a13 a5 d5 22 26 19 18 p06 a_d6 a14 a6 d6 5 13 6 5 p07 a_d7 a15 a7 d7 23 27 20 19 vss0 vss0 connect to 0v 2 10 3 2 vss1 vss1 connect to 0v 25 29 22 21 vdd0 vdd0 connect to 5.0v (port power) 1 9 2 1 vdd1 vdd1 connect to 5.0v (logic power) table 25-1 pin description in eprom mode
hms81c2232/48 hms81c2332/48 114 feb. 2003 ver 1.00 preliminary figure 25-2 timing diagram in program (write & verify) mode figure 25-3 timing diagram in read mode vpp ctl0/1 ~ ~ high 8bit ha la data in data ~ ~ ~ ~ ~ ~ ~ ~ out la data in data out eprom enable ctl2 ctl3 a_d7~ vdd v dd1h 0v 0v 0v address input low 8bit address input write mode verify low 8bit address input write mode verify a_d0 t vdds t vppr t vpps ~ ~ v dd1h v dd1h v ihp ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t hld1 t hld2 t set1 t dly1 t dly2 t cd1 t cd1 t cd1 t cd1 vpp ctl0/1 high 8bit ha la data la data data eprom enable ctl2 ctl3 a_d7~ vdd v dd2h 0v 0v 0v address input low 8bit address input data a_d0 t vdds t vppr t vpps v dd2h v dd2h v ihp t hld1 t hld2 t set1 t dly1 t dly2 t cd1 t cd2 t cd2 t cd1 ha la output low 8bit address input high 8bit address input low 8bit address input data output data output after input a high address, output data following low address input anothe high address step
hms81c2232/48 hms81c2332/48 feb. 2003 ver 1.00 115 parameter symbol min typ max unit programming supply current i vpp --50ma supply current in eprom mode i vddp --20ma vpp level during programming v ihp 11.2 11.5 11.8 v vdd level in program mode v dd1h 4.8 5.0 5.2 v vdd level in read mode v dd2h -2.7-v ctl3~0 high level in eprom mode v ihc 0.9v dd --v ctl3~0 low level in eprom mode v ilc -- 0.1v dd v a_d7~a_d0 high level in eprom mode v ihad 0.9v dd --v a_d7~a_d0 low level in eprom mode v ilad -- 0.1v dd v vdd saturation time t vdds 1- -ms vpp setup time t vppr --1ms vpp saturation time t vpps 1- -ms eprom enable setup time after data input t set1 500 ns eprom enable hold time after t set1 t hld1 500 ns eprom enable delay time after t hld1 t dly1 500 ns eprom enable hold time in write mode t hld2 100 us eprom enable delay time after t hld2 t dly2 500 ns ctl2,1 setup time after low address input and data input t cd1 100 ns ctl1 setup time before data output in read and verify mode t cd2 100 ns table 25-2 ac/dc requirements for program/read mode
hms81c2232/48 hms81c2332/48 116 feb. 2003 ver 1.00 preliminary figure 25-4 programming flow chart start set vdd=v dd1h set vpp=v ihp verify blank first address location eprom write n=1 verify last address apply 3x program cycle 100us program time next address location n ? report programming failure verify of all address vdd=6v & 2.7v report verify failure report programming ok vdd=0v end fail pass pass yes fail no fail yes pass vpp=0v ? verify n=n+1 no

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